| Line 3... |
Line 3... |
module versatile_mem_ctrl_tb
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module versatile_mem_ctrl_tb
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(
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(
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output OK
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output OK
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);
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);
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reg sdram_clk, wb_clk, wb_rst;
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reg wb_clk, wb_rst;
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reg sdram_clk, sdram_rst;
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reg tb_rst;
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wire [31:0] wb0_dat_i;
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wire [31:0] wb0_dat_i;
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wire [3:0] wb0_sel_i;
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wire [3:0] wb0_sel_i;
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wire [31:0] wb0_adr_i;
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wire [31:0] wb0_adr_i;
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wire [2:0] wb0_cti_i;
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wire [2:0] wb0_cti_i;
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| Line 108... |
Line 110... |
.stb(wb0_stb_i),
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.stb(wb0_stb_i),
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.we (wb0_we_i),
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.we (wb0_we_i),
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.ack(wb0_ack_o),
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.ack(wb0_ack_o),
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.clk(wb_clk),
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.clk(wb_clk),
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.dat_i(wb0_dat_o),
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.dat_i(wb0_dat_o),
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.reset(wb_rst)
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.reset(tb_rst)
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);
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);
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wb1_ddr wb1i
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wb1_ddr wb1i
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(
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(
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.adr(wb1_adr_i),
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.adr(wb1_adr_i),
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.bte(wb1_bte_i),
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.bte(wb1_bte_i),
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| Line 123... |
Line 125... |
.stb(wb1_stb_i),
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.stb(wb1_stb_i),
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.we (wb1_we_i),
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.we (wb1_we_i),
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.ack(wb1_ack_o),
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.ack(wb1_ack_o),
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.clk(wb_clk),
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.clk(wb_clk),
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.dat_i(wb1_dat_o),
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.dat_i(wb1_dat_o),
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.reset(wb_rst)
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.reset(tb_rst)
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);
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);
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wb4_ddr wb4i
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wb4_ddr wb4i
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(
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(
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.adr(wb4_adr_i),
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.adr(wb4_adr_i),
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.bte(wb4_bte_i),
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.bte(wb4_bte_i),
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| Line 138... |
Line 140... |
.stb(wb4_stb_i),
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.stb(wb4_stb_i),
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.we (wb4_we_i),
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.we (wb4_we_i),
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.ack(wb4_ack_o),
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.ack(wb4_ack_o),
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.clk(wb_clk),
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.clk(wb_clk),
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.dat_i(wb4_dat_o),
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.dat_i(wb4_dat_o),
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.reset(wb_rst)
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.reset(tb_rst)
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);
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);
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`endif
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`endif
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versatile_mem_ctrl_top # (
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versatile_mem_ctrl_top # (
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.nr_of_wb_clk_domains(2),
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.nr_of_wb_clk_domains(2),
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.nr_of_wb_ports_clk0(2),
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.nr_of_wb_ports_clk0(1),
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.nr_of_wb_ports_clk1(1),
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.nr_of_wb_ports_clk1(1),
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.nr_of_wb_ports_clk2(0),
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.nr_of_wb_ports_clk2(0),
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.nr_of_wb_ports_clk3(0))
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.nr_of_wb_ports_clk3(0))
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dut (
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dut (
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.wb_adr_i_0({{wb0_adr_i[31:2],wb0_we_i,wb0_bte_i,wb0_cti_i},{wb1_adr_i[31:2],wb1_we_i,wb1_bte_i,wb1_cti_i}}),
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.wb_adr_i_0({{wb0_adr_i[31:2],wb0_we_i,wb0_bte_i,wb0_cti_i},{wb1_adr_i[31:2],wb1_we_i,wb1_bte_i,wb1_cti_i}}),
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| Line 278... |
Line 280... |
.rdqs_n(),
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.rdqs_n(),
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.odt()
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.odt()
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);
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);
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`endif
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`endif
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// Wishbone reset
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initial
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initial
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begin
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begin
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#0 wb_rst = 1'b1;
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#0 wb_rst = 1'b1;
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#200 wb_rst = 1'b1;
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#200 wb_rst = 1'b1;
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#200000 wb_rst = 1'b0;
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#200000 wb_rst = 1'b0;
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end
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end
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// SDRAM reset
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initial
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begin
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#0 sdram_rst = 1'b1;
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#200 sdram_rst = 1'b1;
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#200000 sdram_rst = 1'b0;
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end
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// Test bench reset
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initial
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begin
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#0 tb_rst = 1'b1;
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#200 tb_rst = 1'b1;
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//#200000 tb_rst = 1'b0;
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#300000 tb_rst = 1'b0; // hold reset to let initialization complete
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end
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// Wishbone clock
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initial
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initial
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begin
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begin
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#0 wb_clk = 1'b0;
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#0 wb_clk = 1'b0;
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forever
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forever
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#200 wb_clk = !wb_clk; // 25MHz
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//#200 wb_clk = !wb_clk; // 2.5 MHz
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#20 wb_clk = !wb_clk; // 25 MHz
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end
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end
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// SDRAM clock
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initial
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initial
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begin
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begin
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#0 sdram_clk = 1'b0;
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#0 sdram_clk = 1'b0;
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forever
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forever
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#4 sdram_clk = !sdram_clk; // 125MHz
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//#4 sdram_clk = !sdram_clk; // 125 MHz
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#5 sdram_clk = !sdram_clk; // 100 MHz
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end
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end
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endmodule // versatile_mem_ctrl_tb
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endmodule // versatile_mem_ctrl_tb
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