URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb.v] - Diff between revs 80 and 82

Rev 80	Rev 82
Line 319...	Line 319...
`// SDRAM clock`	`// SDRAM clock`
`initial`	`initial`
`begin`	`begin`
`#0 sdram_clk = 1'b0;`	`#0 sdram_clk = 1'b0;`
`forever`	`forever`
`//#4 sdram_clk = !sdram_clk; // 125 MHz`	`#4 sdram_clk = !sdram_clk; // 125 MHz`
`#5 sdram_clk = !sdram_clk; // 100 MHz`	`//#5 sdram_clk = !sdram_clk; // 100 MHz`
`end`	`end`

`endmodule // versatile_mem_ctrl_tb`	`endmodule // versatile_mem_ctrl_tb`

`No newline at end of file`	`No newline at end of file`