Subversion Repositories versatile_mem_ctrl

`include "tb_defines.v"

//`include "tb_defines.v"

   reg         wb_clk, wb_rst;

`ifdef NR_OF_WBM

   reg         sdram_clk, sdram_rst;

        parameter nr_of_wbm = `NR_OF_WBM;

   reg         tb_rst;

`else

        parameter nr_of_wbm = 1;

   wire [31:0] wbm_dat_i [1:nr_of_wbm];

`endif

   wire [3:0]  wbm_sel_i [1:nr_of_wbm];

   wire [31:0] wbm_adr_i [1:nr_of_wbm];

`ifdef SDRAM_CLK_PERIOD

   wire [2:0]  wbm_cti_i [1:nr_of_wbm];

        parameter sdram_clk_period = `SDRAM_CLK_PERIOD;

   wire [1:0]  wbm_bte_i [1:nr_of_wbm];

`else

   wire        wbm_cyc_i [1:nr_of_wbm];

        parameter sdram_clk_period = 8;

   wire        wbm_stb_i [1:nr_of_wbm];

`endif

   wire [31:0] wbm_dat_o [1:nr_of_wbm];

   wire        wbm_ack_o [1:nr_of_wbm];

`ifdef WB_CLK_PERIODS

   wire        wbm_clk   [1:nr_of_wbm];

        parameter [1:nr_of_wbm] wb_clk_periods = {`WB_CLK_PERIODS};

   wire        wbm_rst;

`else

   wire [31:0] wb_sdram_adr_i;

   wire [31:2] wb_sdram_adr_i;

   wire [1:0]  ba, bad;

        genvar i;

`ifdef SDR_16          // SDR SDRAM

`define DUT sdr_sdram_16_ctrl

   wb0 wb0i

`define SDR 16

     (

`ifdef SDR

      .adr(wb0_adr_i),

        wire [1:0]  ba, ba_pad;

      .bte(wb0_bte_i),

        wire [12:0] a, a_pad;

      .cti(wb0_cti_i),

        wire [`SDR-1:0] dq_i, dq_o, dq_pad;

      .cyc(wb0_cyc_i),

        wire        dq_oe;

      .dat(wb0_dat_i),

        wire [1:0]  dqm, dqm_pad;

      .sel(wb0_sel_i),

        wire        cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad;

      .stb(wb0_stb_i),

      .we (wb0_we_i),

        assign #1 {ba_pad,a_pad} = {ba,a};

      .ack(wb0_ack_o),

        assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we};

      .clk(wb_clk),

        assign #1 dqm_pad = dqm;

      .dat_i(wb0_dat_o),

        assign #1 cke_pad = cke;

      .reset(wb_rst)

        assign cs_n_pad = cs_n;

      );

   wb1 wb1i

        mt48lc16m16a2 mem(

     (

                .Dq(dq_pad),

      .adr(wb1_adr_i),

                .Addr(a_pad),

      .bte(wb1_bte_i),

                .Ba(ba_pad),

      .cti(wb1_cti_i),

                .Clk(wb_sdram_clk),

      .cyc(wb1_cyc_i),

                .Cke(cke_pad),

      .dat(wb1_dat_i),

                .Cs_n(cs_n_pad),

      .sel(wb1_sel_i),

                .Ras_n(ras_pad),

      .stb(wb1_stb_i),

                .Cas_n(cas_pad),

      .we (wb1_we_i),

                .We_n(we_pad),

      .ack(wb1_ack_o),

                .Dqm(dqm_pad));

      .clk(wb_clk),

      .dat_i(wb1_dat_o),

                assign #1 dq_pad = (dq_oe) ? dq_o : {`SDR{1'bz}};

      .reset(wb_rst)

                assign #1 dq_i = dq_pad;

      );

   wb4 wb4i

        `DUT DUT(

     (

        // wisbone i/f

      .adr(wb4_adr_i),

        .dat_i(wb_sdram_dat_i),

      .bte(wb4_bte_i),

        .adr_i({wb_sdram_adr_i[24:2],1'b0}),

      .cti(wb4_cti_i),

        .sel_i(wb_sdram_sel_i),

      .cyc(wb4_cyc_i),

        .cti_i(wb_sdram_cti_i),

      .dat(wb4_dat_i),

        .bte_i(wb_sdram_bte_i),

      .sel(wb4_sel_i),

        .we_i (wb_sdram_we_i),

      .stb(wb4_stb_i),

        .cyc_i(wb_sdram_cyc_i),

      .we (wb4_we_i),

        .stb_i(wb_sdram_stb_i),

      .ack(wb4_ack_o),

        .dat_o(wb_sdram_dat_o),

      .clk(wb_clk),

        .ack_o(wb_sdram_ack_o),

      .dat_i(wb4_dat_o),

        // SDR SDRAM

      .reset(wb_rst)

        .ba(ba),

      );

        .a(a),

`endif

        .cmd({ras, cas, we}),

        .cke(cke),

`ifdef DDR_16          // DDR2 SDRAM

        .cs_n(cs_n),

   wb0_ddr wb0i

        .dqm(dqm),

   .cke_pad_o(cke),

        // system

`endif

        .clk(wb_sdram_clk), .rst(wb_sdram_rst));

`ifdef DDR_16

// wishbone master(s)

   assign #1 dqmd = dqm;

generate

   assign    ck_fb_i = ck_fb_o;

        for (i=1; i <= nr_of_wbm; i=i+1) begin: wb_master

`endif

   assign #1 ad = a;

    end

   assign #1 bad = ba;

endgenerate

`ifdef SDR_16          // SDR SDRAM Simulation model

`define SINGLE_WB

mt48lc16m16a2 sdram

`ifdef SINGLE_WB

  (

        assign wb_sdram_dat_i=wbm_b_dat_o[1];

   .Dq(dq_io),

        assign wb_sdram_sel_i=wbm_b_sel_o[1];

   .Addr(ad),

        assign wb_sdram_adr_i=wbm_b_adr_o[1];

   .Ba(bad),

        assign wb_sdram_we_i =wbm_b_we_o[1];

   .Clk(sdram_clk),

        assign wb_sdram_bte_i=wbm_b_bte_o[1];

   .Cke(cked),

        assign wb_sdram_cti_i=wbm_b_cti_o[1];

   .Cs_n(cs_nd),

        assign wb_sdram_cyc_i=wbm_b_cyc_o[1];

   .Ras_n(rasd),

        assign wb_sdram_stb_i=wbm_b_stb_o[1];

   .Cas_n(casd),

        assign wbm_b_dat_i[1]=wb_sdram_dat_o;

   .We_n(wed),

        assign wbm_b_ack_i[1]=wb_sdram_ack_o;

        #0      wb_rst = 1'b1;

                #0      wbm_a_rst[i] = 1'b1;

        #200    wb_rst = 1'b1;

                #200    wbm_a_rst[i] = 1'b0;

   // SDRAM reset

                // Wishbone clock

        #0      sdram_rst = 1'b1;

                #0 wbm_a_clk[i] = 1'b0;

        #200    sdram_rst = 1'b1;

                forever

        #200000 sdram_rst = 1'b0;

                        #(wb_clk_period/2) wbm_a_clk[i] = !wbm_a_clk[i];

   // Test bench reset

   // Wishbone clock

   // SDRAM reset

        #0 wb_clk = 1'b0;

        #0      wb_sdram_rst = 1'b1;

        forever

        #200    wb_sdram_rst = 1'b0;

        #0 sdram_clk = 1'b0;

        #0 wb_sdram_clk = 1'b0;

          #(sdram_clk_period/2) sdram_clk = !sdram_clk;

          #(sdram_clk_period/2) wb_sdram_clk = !wb_sdram_clk;