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sdr_sdram_16_ctrl_actel.v:
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VLIB_BASE = vmemctrl_vl_
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vppreproc --noline --noblank +define+RFR_LENGTH+10 +define+RFR_WRAP_VALUE+1001 +define+ACTEL sdr_sdram_16_ctrl.v > sdr_sdram_16_ctrl_actel.v
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VLIB_DEFINES = +define+BASE+$(VLIB_BASE)
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VLIB_DEFINES += +define+WB3WB3_BRIDGE
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VLIB_DEFINES += +define+WB3_ARBITER_TYPE1
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VLIB_DEFINES += +define+CNT_LFSR_ZQ
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VLIB_DEFINES += +define+DELAY_EMPTYFLAG
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VLIB_DEFINES += +define+DFF_CE_CLEAR
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VLIB_DEFINES += +define+WB_B3_RAM_BE
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#VLIB_DEFINES += +define+SYSTEMVERILOG
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VLIB_ALTERA = vmemctrl_vl_altera.v
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VLIB_ACTEL = vmemctrl_vl_actel.v
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VLIB = versatile_library.v
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VLIB += $(VLIB_ALTERA)
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VLIB += $(VLIB_ACTEL)
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RTL_FILES = versatile_mem_ctrl_defines.v
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RTL_FILES += sdr_sdram_ctrl.v
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RTL_FILES += versatile_mem_ctrl_top.v
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OUT_FILE = vmemctrl.v
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VCOUNT_FILES = VersatileCounter.class.php
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VCOUNT_FILES += VersatileCounter.php
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$(VCOUNT_FILES):
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for file in $(VCOUNT_FILES) ; do \
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svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/misc/$$file ; \
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done
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refresh: $(VCOUNT_FILES)
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./VersatileCounter.php 10 1000
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./VersatileCounter.php 9 500
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./VersatileCounter.php 11 1172
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./VersatileCounter.php 10 586
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./VersatileCounter.php 11 1954
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./VersatileCounter.php 10 977
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./VersatileCounter.php 12 2079
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./VersatileCounter.php 11 1040
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./VersatileCounter.php 12 2407
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./VersatileCounter.php 11 1204
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export:
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export:
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svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v
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svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v
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vppreproc --noline --noblank +define+ALTERA $(VLIB_DEFINES) versatile_library.v | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(VLIB_ALTERA)
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vppreproc --noline --noblank +define+ACTEL $(VLIB_DEFINES) versatile_library.v | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(VLIB_ACTEL)
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config:
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configurator versatile_mem_ctrl_defines.v
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versatile_mem_ctrl: config
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vppreproc --simple +define+VLBASE+$(VLIB_BASE) $(RTL_FILES) | cat copyright.v - > $(OUT_FILE)
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test: versatile_mem_ctrl
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iverilog -tnull lpm_ff.v $(VLIB_ALTERA) $(OUT_FILE)
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iverilog -tnull $(VLIB_ACTEL) $(OUT_FILE)
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# the single all rule
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# the single all rule
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all: sdr_sdram_16_ctrl_actel.v
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all: export versatile_mem_ctrl test
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clean:
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clean:
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rm -rf $(VERSATILE_FIFO_PROJECT_FILES) $(VERSATILE_COUNTER_PROJECT_FILES)
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rm -rf $(VLIB) $(OUT_FILE) $(VCOUNT_FILES)
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rm -rf fifo_fill.v sdr_16.v ddr_16.v
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rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
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rm -rf *_counter.v
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rm -rf *.csv
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rm -rf *~
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rm -rf sdr_sdram_16_ctrl_actel.v
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rm -rf $(VLIB) $(OUT_FILE) $(VCOUNT_FILES)
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