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https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
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Rev 112 |
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Line 114... |
`define BASE versatile_mem_ctrl_
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`define BASE versatile_mem_ctrl_
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// Memory type
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// Memory type
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//=select
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//=select
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//`define RAM // RAM
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//`define RAM // RAM
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`define SDR // SDR
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//`define SDR // SDR
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//`define DDR2 // DDR2
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//`define DDR2 // DDR2
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//`define DDR3 // DDR3
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`define DDR3 // DDR3
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//=end
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//=end
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// Shadow RAM
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// Shadow RAM
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`define SHADOW_RAM
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`define SHADOW_RAM
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`define RAM_MEM_INIT_FILE "ram_init.v"
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`define RAM_MEM_INIT_FILE "ram_init.v"
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`ifdef RAM
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`ifdef RAM
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`define WB_ADR_SIZE `RAM_ADR_SIZE
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`define WB_ADR_SIZE `RAM_ADR_SIZE
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`endif
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`endif
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`ifdef SHADOW_RAM
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`define WB_RAM_ADR_SIZE `RAM_ADR_SIZE
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`endif
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//=tab SDR SDRAM
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//=tab SDR SDRAM
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// External data bus size
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// External data bus size
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`define SDR_EXT_DAT_SIZE 16
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`define SDR_EXT_DAT_SIZE 16
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`ifdef SDR
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`ifdef SDR
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`ifdef SDR_SDRAM_DATA_WIDTH_16
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`ifdef SDR_SDRAM_DATA_WIDTH_16
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`define WB_ADR_SIZE `SDR_BA_SIZE+`SDR_COL_SIZE+`SDR_ROW_SIZE+1
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`define WB_ADR_SIZE `SDR_BA_SIZE+`SDR_COL_SIZE+`SDR_ROW_SIZE+1
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`endif
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`endif
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`endif
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`endif
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//=tab DDR2 SDRAM
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//=tab DDR2 SDRAM
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// Use existing Avalon compatible IP
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// Use existing Avalon compatible IP
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`define DDR2_AVALON
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`define DDR2_AVALON
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// IP module name
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// IP module name
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`define DDR2_IP_NAME ALTERA_DDR2
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`define DDR2_IP_NAME ALTERA_DDR2
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`ifdef DDR2
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`define WB_ADR_SIZE 24
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`endif
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//=tab DDR3 SDRAM
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// Board
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//=select
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`define DDR3_BOARD_2AGX125N // ARRIAII BOARD 2AGX125N
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//=end
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`ifdef DDR3
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`ifdef DDR3_BOARD_2AGX125N
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`define WB_ADR_SIZE 30
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`endif
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`endif
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