URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [sim/] [rtl_sim/] [bin/] [sim_altera.tcl] - Diff between revs 15 and 19

Rev 15	Rev 19
Line 1...	Line 1...
`# Usage:`	`# Usage:`
`# cd /versatile_mem_ctrl/trunk/sim/rtl_sim/run/`	`# cd /versatile_mem_ctrl/trunk/sim/rtl_sim/run/`
`# vsim -gui -do ../bin/sim_altera.tcl`	`# vsim -gui -do ../bin/sim_altera.tcl`

`set DESIGN_NAME "versatile_memory_controller"`	`set DESIGN_NAME "versatile_memory_controller"`
`set WAVE_FILE wave_ddr.do`	`set WAVE_FILE ../bin/wave_ddr.do`
`set FORCE_LIBRARY_RECOMPILE 0`	`set FORCE_LIBRARY_RECOMPILE 0`

`# Quit simulation if you are running one`	`# Quit simulation if you are running one`
`quit -sim`	`quit -sim`

Line 51...	Line 51...

`# Open signal viewer`	`# Open signal viewer`
`view signals`	`view signals`

`# Run the .do file to load signals to the waveform viewer`	`# Run the .do file to load signals to the waveform viewer`
`#do $WAVE_FILE`	`do $WAVE_FILE`

`# Run the simulation`	`# Run the simulation`
`run 330 us`	`run 330 us`


`No newline at end of file`	`No newline at end of file`