| Line 18... |
Line 18... |
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# Compile Altera libraries
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# Compile Altera libraries
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if {![file exists altera_primitives] || $FORCE_LIBRARY_RECOMPILE} {
|
if {![file exists altera_primitives] || $FORCE_LIBRARY_RECOMPILE} {
|
vlib altera_primitives
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vlib altera_primitives
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vmap altera_primitives altera_primitives
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vmap altera_primitives altera_primitives
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vcom -work altera_primitives /opt/altera9.0/quartus/eda/sim_lib/altera_primitives_components.vhd
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vcom -work altera_primitives /opt/altera9.1/quartus/eda/sim_lib/altera_primitives_components.vhd
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vcom -work altera_primitives /opt/altera9.0/quartus/eda/sim_lib/altera_primitives.vhd
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vcom -work altera_primitives /opt/altera9.1/quartus/eda/sim_lib/altera_primitives.vhd
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}
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}
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if {![file exists altera_mf] || $FORCE_LIBRARY_RECOMPILE} {
|
if {![file exists altera_mf] || $FORCE_LIBRARY_RECOMPILE} {
|
vlib altera_mf
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vlib altera_mf
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vmap altera_mf altera_mf
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vmap altera_mf altera_mf
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vcom -work altera_mf /opt/altera9.0/quartus/eda/sim_lib/altera_mf_components.vhd
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vcom -work altera_mf /opt/altera9.1/quartus/eda/sim_lib/altera_mf_components.vhd
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vcom -work altera_mf /opt/altera9.0/quartus/eda/sim_lib/altera_mf.vhd
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vcom -work altera_mf /opt/altera9.1/quartus/eda/sim_lib/altera_mf.vhd
|
|
}
|
|
if {![file exists lpm] || $FORCE_LIBRARY_RECOMPILE} {
|
|
vlib lpm
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|
vmap lpm lpm
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|
vlog -work lpm /opt/altera9.1/quartus/eda/sim_lib/220model.v
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}
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}
|
|
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# Compile project source code
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# Compile project source code
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vlog ../../../rtl/verilog/versatile_mem_ctrl_ip.v +incdir+../../../rtl/verilog/
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vlog ../../../rtl/verilog/versatile_mem_ctrl_ip.v +incdir+../../../rtl/verilog/
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|
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| Line 42... |
Line 47... |
|
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# Invoke the simulator
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# Invoke the simulator
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# -gui Open the GUI without loading a design
|
# -gui Open the GUI without loading a design
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# -novopt Force incremental mode (pre-6.0 behavior)
|
# -novopt Force incremental mode (pre-6.0 behavior)
|
# -L Search library for design units instantiated from Verilog and for VHDL default component binding
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# -L Search library for design units instantiated from Verilog and for VHDL default component binding
|
vsim -gui -novopt -L altera_mf work.versatile_mem_ctrl_tb
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vsim -gui -novopt -L altera_mf -L lpm work.versatile_mem_ctrl_tb
|
|
|
# Open waveform viewer
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# Open waveform viewer
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view wave -title "${DESIGN_NAME}"
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view wave -title "${DESIGN_NAME}"
|
|
|
# Open signal viewer
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# Open signal viewer
|
