| Line 1... |
Line 1... |
onerror {resume}
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -expand -group {CLOCK & RESET} -divider Reset
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add wave -noupdate -group {CLOCK & RESET} -divider Reset
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/wb_rst
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add wave -noupdate -group {CLOCK & RESET} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
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add wave -noupdate -expand -group {CLOCK & RESET} -divider Clocks
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add wave -noupdate -group {CLOCK & RESET} -divider Clocks
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/wb_clk
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add wave -noupdate -group {CLOCK & RESET} -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_clk
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
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add wave -noupdate -expand -group {CLOCK & RESET} -divider {DCM/PLL generated clocks}
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add wave -noupdate -group {CLOCK & RESET} -divider {DCM/PLL generated clocks}
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_0
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_0
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_90
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_90
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_180
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_180
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270
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add wave -noupdate -group DCM/PLL -divider {Xilinx DCM or Altera altpll}
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add wave -noupdate -group DCM/PLL -divider {Xilinx DCM or Altera altpll}
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/rst
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/rst
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk_in
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk_in
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_in
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_in
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk0_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk0_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk90_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk90_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk180_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk180_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
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add wave -noupdate -group {WISHBONE IF} -divider {Clock & reset}
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
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add wave -noupdate -group {WISHBONE IF} -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_clk
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add wave -noupdate -group {WISHBONE IF} -divider wb0
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add wave -noupdate -group {WISHBONE IF} -divider wb0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs0_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs0_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs0_sel_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs0_cti_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs0_bte_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_0
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_we_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_cyc_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_stb_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs0_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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add wave -noupdate -group {WISHBONE IF} -divider wb1
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add wave -noupdate -group {WISHBONE IF} -divider wb1
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs1_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs1_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs1_sel_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_stb_i_1
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs1_cti_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_cyc_i_1
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs1_bte_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_ack_o_1
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_we_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_1
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_cyc_i
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add wave -noupdate -group {WISHBONE IF} -divider wb2
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_stb_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_2
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs1_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_2
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_2
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_2
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_2
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_2
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add wave -noupdate -group {WISHBONE IF} -divider wb3
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_3
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_3
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_3
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_3
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3
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add wave -noupdate -group {WISHBONE IF} -divider Testbench
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb0_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
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add wave -noupdate -group {WISHBONE IF} -divider wb4
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs4_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb1_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs4_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs4_sel_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs4_cti_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs4_bte_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_we_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_cyc_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_stb_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs4_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb4_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
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add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
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add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/rst
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/a_clk
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/tx_fifo/a_dat_i
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {TX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/tx_fifo/a_fifo_full_o
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {TX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/tx_fifo/a_fifo_sel_i
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[27]}
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/a_we_i
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/b_clk
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/tx_fifo/b_dat_o
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {TX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/tx_fifo/b_fifo_empty_o
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[23]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/b_fifo_sel_i
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[22]}
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/b_re_i
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[21]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/dpram_a_a
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[20]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/dpram_a_b
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[19]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/radr0
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[18]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/radr1
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[17]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/radr4
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[16]}
|
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO 0}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[15]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[15]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[14]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[14]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[13]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[13]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[12]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[12]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[11]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[11]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[10]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[10]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[9]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[9]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[8]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[8]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[7]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[7]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[6]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[6]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[5]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[5]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[4]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[4]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[3]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[3]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[2]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[2]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[1]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[1]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[0]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[0]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -divider FIFO_1_1
|
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO 1}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[31]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[47]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[30]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[46]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[29]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[45]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[28]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[44]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[27]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[43]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[26]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[42]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[25]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[41]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[24]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[40]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[23]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[39]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[22]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[38]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[21]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[37]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[20]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[36]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[19]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[35]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[18]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[34]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[17]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[33]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[16]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[32]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -divider FIFO_1_0
|
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO 4}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[15]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[143]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[14]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[142]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[13]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[141]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[12]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[140]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[11]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[139]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[10]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[138]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[9]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[137]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[8]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[136]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[7]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[135]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[6]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[134]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[5]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[133]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[4]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[132]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[3]}
|
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[131]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[130]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[129]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[128]}
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd
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| Line 134... |
Line 142... |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_sel
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_sel
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/sdram_clk
|
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]}
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]}
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o
|
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle
|
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/cur_row
|
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_n_pad_o
|
add wave -noupdate -group {MAIN STATE MACHINE} -divider
|
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/cke_pad_o
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
|
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/cs_n_pad_o
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
|
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/ras_pad_o
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/ba_pad_o
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Literal -radix decimal /versatile_mem_ctrl_tb/dut/addr_pad_o
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_o
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dq_oe
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dq_en
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dqs_en
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/rdqs_n_pad_i
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dqm_en
|
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add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/dqm_o
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add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/dm_rdqs_pad_io
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM}
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM}
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck_n
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck_n
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cke
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cke
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| Line 173... |
Line 166... |
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dm_rdqs
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dm_rdqs
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/dq
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/dq
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO Control}
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/rx_fifo_full
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/rx_fifo_empty
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 0}
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 0}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[7]}
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add wave -noupdate -group {RX FIFO} -divider Control
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[6]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/d
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[5]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[4]}
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write_enable
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[3]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[2]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[1]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[0]}
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read_enable
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add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/wadr0
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk2
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add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/radr0
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst2
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_full
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/q
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_empty
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add wave -noupdate -group {RX FIFO} -divider FIFO_0_1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[27]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[23]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[22]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[21]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[20]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[19]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[18]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[17]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[16]}
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add wave -noupdate -group {RX FIFO} -divider FIFO_0_0
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[15]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[14]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[13]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[12]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[11]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[10]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[9]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[8]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[7]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[6]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[5]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[4]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[3]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[2]}
|
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[1]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[0]}
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 1}
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 1}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[39]}
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add wave -noupdate -group {RX FIFO} -divider Control
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[38]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/d
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[37]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[36]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write_enable
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[35]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[34]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[33]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[32]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read_enable
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add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/wadr1
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk2
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add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/radr1
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst2
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 4}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_full
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[143]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/q
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[142]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_empty
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[141]}
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add wave -noupdate -group {RX FIFO} -divider FIFO_1_1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[140]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[139]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[138]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[137]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[136]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[27]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[135]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[134]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[133]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[132]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[23]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[131]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[22]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[130]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[21]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[129]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[20]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[128]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[19]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/wadr4
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[18]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/radr4
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[17]}
|
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[16]}
|
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
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add wave -noupdate -group {RX FIFO} -divider FIFO_1_0
|
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[15]}
|
add wave -noupdate -group {BURST LENGTH} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[14]}
|
add wave -noupdate -group {BURST LENGTH} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[13]}
|
add wave -noupdate -group {BURST LENGTH} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[12]}
|
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[11]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[10]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[9]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[8]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[7]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[6]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[5]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[4]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[3]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[2]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[1]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[0]}
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/write
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/write
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/read
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/read
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
|
| Line 237... |
Line 275... |
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
|
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add wave -noupdate -expand -group {DDR2 IF} -divider FSM
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
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add wave -noupdate -expand -group {DDR2 IF} -divider {Controller side}
|
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add wave -noupdate -expand -group {DDR2 IF} -divider {Clock & reset}
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
|
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add wave -noupdate -expand -group {DDR2 IF} -divider {Tx Data}
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
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add wave -noupdate -expand -group {DDR2 IF} -divider {Rx Data}
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o
|
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add wave -noupdate -expand -group {DDR2 IF} -divider {SDRAM side}
|
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add wave -noupdate -expand -group {DDR2 IF} -divider Address
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/ba_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/addr_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -divider {Data & mask}
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dm_rdqs_pad_io
|
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add wave -noupdate -expand -group {DDR2 IF} -divider {Clock & strobe}
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cke_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_n_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_i
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/dqs_oe
|
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add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_pad_io
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_n_pad_io
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/rdqs_n_pad_i
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider Command
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cs_n_pad_o
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ras_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/wb_rst
|
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add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
|
add wave -noupdate -divider {New Divider}
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
|
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add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
|
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add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
|
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add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
|
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add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
|
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add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
|
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add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
|
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
|
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add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
|
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add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
|
|
add wave -noupdate -divider TEMP
|
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o
|
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_i
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_we
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_reg
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_dly
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_dly
|
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add wave -noupdate -divider tmp
|
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/wb_dat_i_v
|
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/wb_dat_i
|
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_fifo_di
|
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/d
|
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add wave -noupdate -divider tmp
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/d
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/write
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/write_enable
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/clk1
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/rst1
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_adr
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_data
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_enable
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/clk2
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/rst2
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_full
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/q
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_empty
|
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add wave -noupdate -divider
|
|
add wave -noupdate -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/fifo_rd_adr
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_o
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_tx
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_tx_reg
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_o
|
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
WaveRestoreCursors {{Cursor 1} {252260000 ps} 0}
|
WaveRestoreCursors {{Cursor 1} {286644100 ps} 0}
|
configure wave -namecolwidth 371
|
configure wave -namecolwidth 287
|
configure wave -valuecolwidth 84
|
configure wave -valuecolwidth 136
|
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
configure wave -signalnamewidth 0
|
configure wave -signalnamewidth 0
|
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
configure wave -datasetprefix 0
|
configure wave -datasetprefix 0
|
configure wave -rowmargin 4
|
configure wave -rowmargin 4
|
| Line 253... |
Line 379... |
configure wave -gridperiod 1
|
configure wave -gridperiod 1
|
configure wave -griddelta 40
|
configure wave -griddelta 40
|
configure wave -timeline 0
|
configure wave -timeline 0
|
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
update
|
update
|
WaveRestoreZoom {193310526 ps} {259935789 ps}
|
WaveRestoreZoom {286559678 ps} {286728522 ps}
|
WaveRestoreZoom {286559678 ps} {286728522 ps}
|
WaveRestoreZoom {286559678 ps} {286728522 ps}
|
