| Line 19... |
Line 19... |
add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk180_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk180_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
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add wave -noupdate -group {WISHBONE IF} -divider {Clock & reset}
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add wave -noupdate -group {WISHBONE IF} -divider {Clock & reset}
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
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add wave -noupdate -group {WISHBONE IF} -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_clk
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_clk
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add wave -noupdate -group {WISHBONE IF} -divider wb0
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add wave -noupdate -group {WISHBONE IF} -divider wb0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_0
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add wave -noupdate -group {WISHBONE IF} -format Logic {/versatile_mem_ctrl_tb/dut/wb_stb_i_0[1]}
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add wave -noupdate -group {WISHBONE IF} -format Logic {/versatile_mem_ctrl_tb/dut/wb_cyc_i_0[1]}
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add wave -noupdate -group {WISHBONE IF} -format Logic {/versatile_mem_ctrl_tb/dut/wb_ack_o_0[1]}
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0
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add wave -noupdate -group {WISHBONE IF} -divider wb1
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add wave -noupdate -group {WISHBONE IF} -divider wb1
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_stb_i_1
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_stb_i_1
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| Line 50... |
Line 53... |
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_3
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_3
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3
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add wave -noupdate -group {WISHBONE IF} -divider Testbench
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add wave -noupdate -group {WISHBONE IF} -divider Testbench
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb0_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/wb0_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb1_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/wb1_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb4_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/wb4_ack_o
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add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
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add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
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| Line 94... |
Line 101... |
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[4]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[4]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[3]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[3]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[2]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[2]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[1]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[1]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[0]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[0]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -divider FIFO_1_1
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[27]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[27]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[23]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[23]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[22]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[22]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[21]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[21]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[20]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[20]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[19]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[19]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[18]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[18]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[17]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[17]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[16]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[16]}
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[15]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -divider FIFO_1_0
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[14]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[15]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[13]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[14]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[12]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[13]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[11]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[12]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[10]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[11]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[9]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[10]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[8]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[9]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[7]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[8]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[6]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[7]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[5]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[6]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[4]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[5]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[3]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[4]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[3]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]}
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]}
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
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add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
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| Line 275... |
Line 280... |
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
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add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
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add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
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add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
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add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
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add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
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add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
|
add wave -noupdate -expand -group {DDR2 IF} -divider FSM
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add wave -noupdate -group {DDR2 IF} -divider FSM
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
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add wave -noupdate -expand -group {DDR2 IF} -divider {Controller side}
|
add wave -noupdate -group {DDR2 IF} -divider {Controller side}
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Clock & reset}
|
add wave -noupdate -group {DDR2 IF} -divider {Clock & reset}
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
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add wave -noupdate -expand -group {DDR2 IF} -divider {Tx Data}
|
add wave -noupdate -group {DDR2 IF} -divider {Tx Data}
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Rx Data}
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add wave -noupdate -group {DDR2 IF} -divider {Rx Data}
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o
|
add wave -noupdate -expand -group {DDR2 IF} -divider {SDRAM side}
|
add wave -noupdate -group {DDR2 IF} -divider {SDRAM side}
|
add wave -noupdate -expand -group {DDR2 IF} -divider Address
|
add wave -noupdate -group {DDR2 IF} -divider Address
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/ba_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/ba_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/addr_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/addr_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Data & mask}
|
add wave -noupdate -group {DDR2 IF} -divider {Data & mask}
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dm_rdqs_pad_io
|
add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dm_rdqs_pad_io
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Clock & strobe}
|
add wave -noupdate -group {DDR2 IF} -divider {Clock & strobe}
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cke_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cke_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_n_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_n_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_i
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_i
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/dqs_oe
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/dqs_oe
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_pad_io
|
add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_pad_io
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_n_pad_io
|
add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_n_pad_io
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/rdqs_n_pad_i
|
add wave -noupdate -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/rdqs_n_pad_i
|
add wave -noupdate -expand -group {DDR2 IF} -divider Command
|
add wave -noupdate -group {DDR2 IF} -divider Command
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cs_n_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cs_n_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ras_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ras_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/wb_rst
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/wb_rst
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
add wave -noupdate -divider {New Divider}
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
|
add wave -noupdate -divider TEMP
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_i
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_we
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_reg
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_dly
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_dly
|
|
add wave -noupdate -divider tmp
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/wb_dat_i_v
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/wb_dat_i
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_fifo_di
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/d
|
|
add wave -noupdate -divider tmp
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/d
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/write
|
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add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/write_enable
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/clk1
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/rst1
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_adr
|
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_data
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_enable
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/clk2
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/rst2
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_full
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/q
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_empty
|
|
add wave -noupdate -divider
|
|
add wave -noupdate -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
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add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/fifo_rd_adr
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_o
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_tx
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_tx_reg
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add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_o
|
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TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
WaveRestoreCursors {{Cursor 1} {286644100 ps} 0}
|
WaveRestoreCursors {{Cursor 1} {287800000 ps} 0}
|
configure wave -namecolwidth 287
|
configure wave -namecolwidth 321
|
configure wave -valuecolwidth 136
|
configure wave -valuecolwidth 121
|
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
configure wave -signalnamewidth 0
|
configure wave -signalnamewidth 0
|
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
configure wave -datasetprefix 0
|
configure wave -datasetprefix 0
|
configure wave -rowmargin 4
|
configure wave -rowmargin 4
|
| Line 379... |
Line 345... |
configure wave -gridperiod 1
|
configure wave -gridperiod 1
|
configure wave -griddelta 40
|
configure wave -griddelta 40
|
configure wave -timeline 0
|
configure wave -timeline 0
|
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
update
|
update
|
WaveRestoreZoom {286559678 ps} {286728522 ps}
|
WaveRestoreZoom {0 ps} {346500 ns}
|
WaveRestoreZoom {0 ps} {346500 ns}
|
WaveRestoreZoom {0 ps} {346500 ns}
|
