| Line 20... |
Line 20... |
add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
|
add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
|
add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
|
add wave -noupdate -group {WISHBONE IF} -divider {Clock & reset}
|
add wave -noupdate -group {WISHBONE IF} -divider {Clock & reset}
|
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
|
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
|
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_clk
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_clk
|
add wave -noupdate -group {WISHBONE IF} -divider wb0
|
add wave -noupdate -group {WISHBONE IF} -divider
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_0
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_0
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_0
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add wave -noupdate -group {WISHBONE IF} -format Logic {/versatile_mem_ctrl_tb/dut/wb_stb_i_0[1]}
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Logic {/versatile_mem_ctrl_tb/dut/wb_stb_i_0[1]}
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add wave -noupdate -group {WISHBONE IF} -format Logic {/versatile_mem_ctrl_tb/dut/wb_cyc_i_0[1]}
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Logic {/versatile_mem_ctrl_tb/dut/wb_cyc_i_0[1]}
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add wave -noupdate -group {WISHBONE IF} -format Logic {/versatile_mem_ctrl_tb/dut/wb_ack_o_0[1]}
|
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Logic {/versatile_mem_ctrl_tb/dut/wb_ack_o_0[1]}
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0
|
add wave -noupdate -group {WISHBONE IF} -divider wb1
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add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -divider
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1
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add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1
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add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_stb_i_1
|
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Logic /versatile_mem_ctrl_tb/dut/wb_stb_i_1
|
add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_cyc_i_1
|
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Logic /versatile_mem_ctrl_tb/dut/wb_cyc_i_1
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_ack_o_1
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add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Logic /versatile_mem_ctrl_tb/dut/wb_ack_o_1
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_1
|
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_1
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add wave -noupdate -group {WISHBONE IF} -divider wb2
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add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -divider
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_2
|
add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_2
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_2
|
add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_2
|
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_2
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add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_2
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_2
|
add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_2
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_2
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add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_2
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_2
|
add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_2
|
add wave -noupdate -group {WISHBONE IF} -divider wb3
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add wave -noupdate -group {WISHBONE IF} -group wb2 -divider
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_3
|
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_3
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_3
|
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_3
|
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_3
|
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_3
|
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_3
|
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_3
|
add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3
|
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3
|
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3
|
add wave -noupdate -group {WISHBONE IF} -divider Testbench
|
add wave -noupdate -group {WISHBONE IF} -group wb3 -divider
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_adr_i
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_adr_i
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Logic /versatile_mem_ctrl_tb/wb0_ack_o
|
add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/wb0_ack_o
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -divider
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_adr_i
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_adr_i
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
|
add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/wb1_ack_o
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Logic /versatile_mem_ctrl_tb/wb1_ack_o
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -divider
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_adr_i
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
|
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_adr_i
|
add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/wb4_ack_o
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
|
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Logic /versatile_mem_ctrl_tb/wb4_ack_o
|
|
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -divider
|
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
|
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
|
| Line 154... |
Line 156... |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle
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add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/cur_row
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/cur_row
|
add wave -noupdate -group {MAIN STATE MACHINE} -divider
|
add wave -noupdate -group {MAIN STATE MACHINE} -divider
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/burst_mask
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM}
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM}
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck_n
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add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck_n
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cke
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cke
|
| Line 172... |
Line 175... |
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/dq
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/dq
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n
|
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 0}
|
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 0}
|
add wave -noupdate -group {RX FIFO} -divider Control
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/d
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/d
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write_enable
|
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write_enable
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk1
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk1
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst1
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst1
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read_enable
|
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read_enable
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk2
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk2
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst2
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst2
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_full
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_full
|
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/q
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/q
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_empty
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add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_empty
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/d
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add wave -noupdate -group {RX FIFO} -divider FIFO_0_1
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write_enable
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst1
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[27]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read_enable
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk2
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst2
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_full
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[23]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/q
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[22]}
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add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_empty
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[21]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[20]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[19]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[18]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[28]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[17]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[27]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[16]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {RX FIFO} -divider FIFO_0_0
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[15]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[14]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[23]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[13]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[22]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[12]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[21]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[11]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[20]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[10]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[19]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[9]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[18]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[8]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[17]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[7]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[16]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[6]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[15]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[5]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[14]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[4]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[13]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[3]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[12]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[2]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[11]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[1]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[10]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[0]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[9]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[8]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[7]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[6]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[5]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[4]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[3]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[2]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[1]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[0]}
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 1}
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add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 1}
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add wave -noupdate -group {RX FIFO} -divider Control
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/d
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write_enable
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk1
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[27]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst1
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[25]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read_enable
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[24]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk2
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[23]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst2
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[22]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_full
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[21]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/q
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[20]}
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add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_empty
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[19]}
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add wave -noupdate -group {RX FIFO} -divider FIFO_1_1
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[18]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[31]}
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[17]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[30]}
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add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[16]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[29]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[15]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[28]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[14]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[27]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[13]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[26]}
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add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[12]}
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add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[25]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[11]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[24]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[10]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[23]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[9]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[22]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[8]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[21]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[7]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[20]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[6]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[19]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[5]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[18]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[4]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[17]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[3]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[16]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[2]}
|
add wave -noupdate -group {RX FIFO} -divider FIFO_1_0
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[1]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[15]}
|
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[0]}
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[14]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[13]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[12]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[11]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[10]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[9]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[8]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[7]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[6]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[5]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[4]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[3]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[2]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[1]}
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[0]}
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/write
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/write
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/read
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/read
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
|
| Line 280... |
Line 277... |
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
|
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
|
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
|
add wave -noupdate -group {DDR2 IF} -divider FSM
|
add wave -noupdate -group {DDR2 IF} -divider FSM
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
add wave -noupdate -group {DDR2 IF} -divider {Controller side}
|
add wave -noupdate -group {DDR2 IF} -divider {Controller side}
|
add wave -noupdate -group {DDR2 IF} -divider {Clock & reset}
|
add wave -noupdate -group {DDR2 IF} -divider {Clock & reset}
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
|
| Line 319... |
Line 326... |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/wb_rst
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/wb_rst
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
|
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
|
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
|
|
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
WaveRestoreCursors {{Cursor 1} {287800000 ps} 0}
|
WaveRestoreCursors {{Cursor 1} {287500000 ps} 0}
|
configure wave -namecolwidth 321
|
configure wave -namecolwidth 362
|
configure wave -valuecolwidth 121
|
configure wave -valuecolwidth 136
|
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
configure wave -signalnamewidth 0
|
configure wave -signalnamewidth 0
|
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
configure wave -datasetprefix 0
|
configure wave -datasetprefix 0
|
configure wave -rowmargin 4
|
configure wave -rowmargin 4
|
| Line 345... |
Line 342... |
configure wave -gridperiod 1
|
configure wave -gridperiod 1
|
configure wave -griddelta 40
|
configure wave -griddelta 40
|
configure wave -timeline 0
|
configure wave -timeline 0
|
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
update
|
update
|
WaveRestoreZoom {0 ps} {346500 ns}
|
WaveRestoreZoom {287392403 ps} {287565725 ps}
|
WaveRestoreZoom {287392403 ps} {287565725 ps}
|
WaveRestoreZoom {287392403 ps} {287565725 ps}
|
