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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [sim/] [rtl_sim/] [bin/] [wave_ddr.do] - Diff between revs 82 and 86

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Rev 82 Rev 86
Line 262... Line 262...
add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
add wave -noupdate -group {DDR2 IF} -divider FSM
add wave -noupdate -group {DDR2 IF} -divider FSM
add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
 
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270
add wave -noupdate -group {DDR2 IF} -divider {Controller side}
add wave -noupdate -group {DDR2 IF} -divider {Controller side}
add wave -noupdate -group {DDR2 IF} -divider {Clock & reset}
add wave -noupdate -group {DDR2 IF} -divider {Clock & reset}
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
add wave -noupdate -group {DDR2 IF} -divider {Tx Data}
add wave -noupdate -group {DDR2 IF} -divider {Tx Data}
Line 329... Line 330...
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full}
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full}
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag}
add wave -noupdate -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag}
add wave -noupdate -group {FIFO Pointers & Flags} -divider {FIFO Flags on top-level}
add wave -noupdate -group {FIFO Pointers & Flags} -divider {FIFO Flags on top-level}
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_empty
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_empty
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_flag
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_flag
 
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx
 
add wave -noupdate -divider tmp
 
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o
 
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io
 
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270
 
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx
 
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_180
 
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx_reg
 
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_i
TreeUpdate [SetDefaultTree]
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {301340000 ps} 0}
WaveRestoreCursors {{Cursor 1} {222981669 ps} 0}
configure wave -namecolwidth 441
configure wave -namecolwidth 441
configure wave -valuecolwidth 151
configure wave -valuecolwidth 151
configure wave -justifyvalue left
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -snapdistance 10
Line 345... Line 355...
configure wave -gridperiod 1
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timeline 0
configure wave -timelineunits ns
configure wave -timelineunits ns
update
update
WaveRestoreZoom {300901312 ps} {301778688 ps}
WaveRestoreZoom {0 ps} {346500 ns}
WaveRestoreZoom {0 ps} {346500 ns}
WaveRestoreZoom {0 ps} {346500 ns}

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