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#**************************************************************
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#**************************************************************
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# Time Information
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# Time Information
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#**************************************************************
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#**************************************************************
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# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16 -5E)
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# Clock cycle time: min=5.00ns, max=8.00ns
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set tCK 5.000
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# Input setup time: tISb=350ps, tISa=600ps
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set tSU 0.600
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# Input hold time: tIHb=470ps, tIHa=600ps
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set tH 0.600
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# DQS output access time from CK/CK#
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set tDQSCKmin -0.500
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set tDQSCKmax 0.500
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# DQ output access time from CK/CK#
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set tACmin -0.600
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set tACmax 0.600
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#**************************************************************
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#**************************************************************
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# Create Clock
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# Create Clock
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#**************************************************************
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#**************************************************************
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# Clock frequency
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# Clock frequency
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set wb_clk_period 20.000
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set wb_clk_period 20.000
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set sdram_clk_period 8.000
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set sdram_clk_period $tCK
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# Clocks
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# Clocks
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create_clock -name {wb_clk} -period $wb_clk_period
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create_clock -name {wb_clk} -period $wb_clk_period [get_ports {wb_clk}]
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create_clock -name {sdram_clk} -period $sdram_clk_period
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create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]
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# Virtual clocks
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# Virtual clocks
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create_clock -name {v_wb_clk_in} -period $wb_clk_period
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create_clock -name {v_wb_clk_in} -period $wb_clk_period
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create_clock -name {v_wb_clk_out} -period $wb_clk_period
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create_clock -name {v_wb_clk_out} -period $wb_clk_period
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create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
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create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
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create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
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create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
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# Base clock for the PLL input clock port
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create_clock -name pll_base_clock -period $sdram_clk_period [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}]
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#**************************************************************
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#**************************************************************
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# Create Generated Clock
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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create_generated_clock -name {sdram_clk_0} -phase 0 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
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create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
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create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
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create_generated_clock -name {sdram_clk_180} -phase 180 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
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create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
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create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*]
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create_generated_clock -name {sdram_clk_270} -phase 270 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
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#derive_pll_clocks
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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set ddr2_input_delay_min 0
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set_input_delay -clock {v_sdram_clk_in} -max $tACmax [get_ports {dq_pad_io[*]}]
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set ddr2_input_delay_max 0
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set_input_delay -clock {v_sdram_clk_in} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {ck_fb_pad_i}]
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set_input_delay -clock {v_sdram_clk_in} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dm_rdqs_pad_io[*]}]
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dq_pad_io[*]}]
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set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}]
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dqs_pad_io[*]}]
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set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dqs_n_pad_io[*]}]
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set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {rdqs_n_pad_i[*]}]
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set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {ck_fb_pad_i}]
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dm_rdqs_pad_io[*]}]
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dq_pad_io[*]}]
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dqs_pad_io[*]}]
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dqs_n_pad_io[*]}]
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set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {rdqs_n_pad_i[*]}]
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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set ddr2_output_delay_min 0
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set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dq_pad_io[*]}]
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set ddr2_output_delay_max 0
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set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_pad_o}]
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set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_n_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cke_pad_o}]
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set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dqs_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_fb_pad_o}]
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set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cs_n_pad_o}]
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set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ras_pad_o}]
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set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cas_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {we_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dm_rdqs_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ba_pad_o[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {addr_pad_o[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dq_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_oe}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_n_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {odt_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_n_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cke_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_fb_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cs_n_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ras_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cas_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {we_pad_o}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dm_rdqs_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ba_pad_o[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {addr_pad_o[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dq_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_oe}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_n_pad_io[*]}]
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set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {odt_pad_o}]
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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#**************************************************************
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#**************************************************************
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# Set False Path
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Reset
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set_false_path -from [get_ports {wb_rst}]
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set_false_path -from [get_ports {wb_rst}]
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# Input Timing Exceptions
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#
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# Output timing Exceptions
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set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out]
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set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out]
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set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out]
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set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out]
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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