| Line 37... |
Line 37... |
create_clock -name {v_wb_clk_in} -period $wb_clk_period
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create_clock -name {v_wb_clk_in} -period $wb_clk_period
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create_clock -name {v_wb_clk_out} -period $wb_clk_period
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create_clock -name {v_wb_clk_out} -period $wb_clk_period
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create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
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create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
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create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
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create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
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#**************************************************************
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#**************************************************************
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# Create Generated Clock
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
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create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
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create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
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create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
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create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
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create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
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create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*]
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create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*]
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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| Line 63... |
Line 68... |
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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set_input_delay -clock {v_sdram_clk_in} -max $tACmax [get_ports {dq_pad_io[*]}]
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set_input_delay -clock {ck_pad_o} -max $tACmax [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}]
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dq_pad_io[*]}]
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set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dqs_pad_io[*]}]
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#set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dqs_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dqs_pad_n_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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| Line 101... |
Line 117... |
# Set False Path
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Reset
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# Reset
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set_false_path -from [get_ports {wb_rst}]
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set_false_path -from [get_ports {wb_rst}]
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# Input Timing Exceptions
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# Input Timing Exceptions
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#
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set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
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# Output timing Exceptions
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set_false_path -setup -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
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set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out]
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set_false_path -hold -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
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set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out]
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set_false_path -hold -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
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set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out]
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set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out]
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# Output Timing Exceptions
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set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
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set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
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set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
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set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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| Line 132... |
Line 153... |
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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# Set Input Transition
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#**************************************************************
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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