| Line 1... |
Line 1... |
#**************************************************************
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#**************************************************************
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# Time Information
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# Timimg Information for DDR2 SDRAM
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#**************************************************************
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#**************************************************************
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# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E)
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# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E)
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# Clock cycle time: min=5.00ns, max=8.00ns
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# Clock cycle time: min=5.00ns, max=8.00ns
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set tCK 5.000
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set tCK 5.000
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# Input setup time: tISb=350ps, tISa=600ps
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# Data Strobe Out
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set tSU 0.600
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# Input hold time: tIHb=470ps, tIHa=600ps
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set tH 0.600
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# DQS output access time from CK/CK#
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# DQS output access time from CK/CK#
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set tDQSCKmin -0.500
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set tDQSCKmin -0.500
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set tDQSCKmax 0.500
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set tDQSCKmax 0.500
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# Data Strobe In
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# DQS rising edge to CK rising edge
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set tDQSSmin [expr -0.25 * $tCK]
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set tDQSSmax [expr 0.25 * $tCK]
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# DQS falling to CK rising: setup time
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set tDSSmin [expr 0.2 * $tCK]
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# DQS falling from CK rising: hold time
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set tDSHmin [expr 0.2 * $tCK]
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# Data Out
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# DQ output access time from CK/CK#
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# DQ output access time from CK/CK#
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set tACmin -0.600
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set tACmin -0.600
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set tACmax 0.600
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set tACmax 0.600
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# Data In
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# DQ and DM input setup time to DQS
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set tDSb 0.150
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# DQ and DM input hold time to DQS
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set tDHb 0.275
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# DQ and DM input setup time to DQS
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set tDSa 0.400
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# DQ and DM input hold time to DQS
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set tDHa 0.400
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# Command and Address
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# Input setup time
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set tISb 0.350
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set tISa 0.600
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# Input hold time
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set tIHb 0.470
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set tIHa 0.600
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#**************************************************************
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# Timimg Information
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#**************************************************************
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# Trace delay for data
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set tTDDmin 0.100
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set tTDDmax 0.200
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# Trace delay for clock
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set tTDCmin 0.100
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set tTDCmax 0.200
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#**************************************************************
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#**************************************************************
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# Create Clock
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# Create Clock
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#**************************************************************
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#**************************************************************
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| Line 32... |
Line 68... |
# Clocks
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# Clocks
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create_clock -name {wb_clk} -period $wb_clk_period [get_ports {wb_clk}]
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create_clock -name {wb_clk} -period $wb_clk_period [get_ports {wb_clk}]
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create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]
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create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]
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# Virtual clocks
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# Virtual clocks
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create_clock -name {v_wb_clk_in} -period $wb_clk_period
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#create_clock -name {v_wb_clk_in} -period $wb_clk_period
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create_clock -name {v_wb_clk_out} -period $wb_clk_period
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#create_clock -name {v_wb_clk_out} -period $wb_clk_period
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create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
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#create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
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create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
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#create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
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#**************************************************************
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#**************************************************************
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# Create Generated Clock
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
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create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
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create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
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create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
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create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
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create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
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create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*]
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create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*]
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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# Set Clock Latency
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| Line 67... |
Line 100... |
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Double Data Rate requires constraints for both rising and falling clock edge
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# Input max delay value = max trace delay for data + tCO of external device – min trace delay for clock
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# Input min delay value = min trace delay for data + tCOmin of external device – max trace delay for clock
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# Assume (for now): max trace delay for data = min trace delay for clock
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# min trace delay for data = max trace delay for clock
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# Data
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set_input_delay -clock {ck_pad_o} -max $tACmax [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -max $tACmax [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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# Data Strobe
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set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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# Data Strobe
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set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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# Data Mask
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set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] -add_delay
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# Single Data Rate requires constraints for rising clock edge only
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_n_pad_io[*]}] -add_delay
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#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Double Data Rate requires constraints for both rising and falling clock edge
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set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dq_pad_io[*]}] -add_delay
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# Output max delay = max trace delay for data + tSU of external register – min trace delay for clock
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set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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# Output min delay = min trace delay for data – tH of external register – max trace delay for clock
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set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dq_pad_io[*]}] -add_delay
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# Assume (for now): max trace delay for data = min trace delay for clock
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set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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# min trace delay for data = max trace delay for clock
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# Data
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#set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dq_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dq_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
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# Data Strobe
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#set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dqs_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dqs_pad_n_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dqs_pad_io[*]}] -add_delay
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#set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
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# Data Strobe
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dqs_n_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
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# Data Mask
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
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# Single Data Rate requires constraints for rising clock edge only
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# Chip Select
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cs_n_pad_o}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cs_n_pad_o}] -add_delay
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# Row Address Strobe
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {ras_pad_o}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {ras_pad_o}] -add_delay
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# Column Address Strobe
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cas_pad_o}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cas_pad_o}] -add_delay
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# Write Enable
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {we_pad_o}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {we_pad_o}] -add_delay
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# Bank Address
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {ba_pad_o[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {ba_pad_o[*]}] -add_delay
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# Address
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {addr_pad_o[*]}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {addr_pad_o[*]}] -add_delay
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# Clock Enable
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set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cke_pad_o}] -add_delay
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set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cke_pad_o}] -add_delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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| Line 119... |
Line 196... |
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# Reset
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# Reset
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set_false_path -from [get_ports {wb_rst}]
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set_false_path -from [get_ports {wb_rst}]
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# Input Timing Exceptions
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# Input Timing Exceptions
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# False path exceptions for opposite-edge transfer
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# Data
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set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
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set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
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set_false_path -setup -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
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set_false_path -setup -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
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set_false_path -hold -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
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set_false_path -hold -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
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set_false_path -hold -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
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set_false_path -hold -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
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# Data Strobe
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#set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0]
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#set_false_path -setup -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0]
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#set_false_path -hold -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0]
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#set_false_path -hold -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0]
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# Output Timing Exceptions
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# Output Timing Exceptions
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# False path exceptions for opposite-edge transfer
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# Data
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set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
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set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
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set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
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set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
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set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
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set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
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set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
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set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
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# Data Strobe
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set_false_path -setup -rise_from [get_clocks sdram_clk_0] -fall_to [get_clocks ck_pad_o]
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set_false_path -setup -fall_from [get_clocks sdram_clk_0] -rise_to [get_clocks ck_pad_o]
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set_false_path -hold -rise_from [get_clocks sdram_clk_0] -rise_to [get_clocks ck_pad_o]
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set_false_path -hold -fall_from [get_clocks sdram_clk_0] -fall_to [get_clocks ck_pad_o]
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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| Line 150... |
Line 241... |
#**************************************************************
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#**************************************************************
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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# Set Input Transition
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#**************************************************************
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#**************************************************************
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