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[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [bin/] [versatile_memory_controller.sdc] - Diff between revs 30 and 81

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Rev 30 Rev 81
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# Timimg Information for DDR2 SDRAM
# Timimg Information for DDR2 SDRAM
#**************************************************************
#**************************************************************
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E)
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E)
 
 
# Clock cycle time: min=5.00ns, max=8.00ns
# Clock cycle time: min=5.00ns, max=8.00ns
set tCK 5.000
set tCK 8.000
 
 
# Data Strobe Out
# Data Strobe Out
# DQS output access time from CK/CK#
# DQS output access time from CK/CK#
set tDQSCKmin -0.500
set tDQSCKmin -0.500
set tDQSCKmax  0.500
set tDQSCKmax  0.500
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# Clock frequency
# Clock frequency
set wb_clk_period 20.000
set wb_clk_period 20.000
set sdram_clk_period $tCK
set sdram_clk_period $tCK
 
 
# Clocks
# Clocks
create_clock -name {wb_clk}    -period $wb_clk_period    [get_ports {wb_clk}]
create_clock -name {wb_clk[*]} -period $wb_clk_period    [get_ports {wb_clk[*]}]
create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]
create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]
 
 
# Virtual clocks
# Virtual clocks
#create_clock -name {v_wb_clk_in}     -period $wb_clk_period
#create_clock -name {v_wb_clk_in}     -period $wb_clk_period
#create_clock -name {v_wb_clk_out}    -period $wb_clk_period
#create_clock -name {v_wb_clk_out}    -period $wb_clk_period
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#**************************************************************
#**************************************************************
# Set False Path
# Set False Path
#**************************************************************
#**************************************************************
 
 
# Reset
# Reset
set_false_path -from [get_ports {wb_rst}]
set_false_path -from [get_ports {wb_rst[*]}]
 
 
# Input Timing Exceptions
# Input Timing Exceptions
# False path exceptions for opposite-edge transfer
# False path exceptions for opposite-edge transfer
# Data
# Data
set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]

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