URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [bin/] [versatile_memory_controller.sdc] - Diff between revs 81 and 83

Rev 81	Rev 83
Line 67...	Line 67...

`# Clocks`	`# Clocks`
`create_clock -name {wb_clk[]} -period $wb_clk_period [get_ports {wb_clk[]}]`	`create_clock -name {wb_clk[]} -period $wb_clk_period [get_ports {wb_clk[]}]`
`create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]`	`create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]`

	`# DQS used as clock`
	`#create_clock -name {dqs_n_pad_io[0]} -period $sdram_clk_period [get_ports {dqs_n_pad_io[0]}]`

`# Virtual clocks`	`# Virtual clocks`
`#create_clock -name {v_wb_clk_in} -period $wb_clk_period`	`#create_clock -name {v_wb_clk_in} -period $wb_clk_period`
`#create_clock -name {v_wb_clk_out} -period $wb_clk_period`	`#create_clock -name {v_wb_clk_out} -period $wb_clk_period`
`#create_clock -name {v_sdram_clk_in} -period $sdram_clk_period`	`#create_clock -name {v_sdram_clk_in} -period $sdram_clk_period`
`#create_clock -name {v_sdram_clk_out} -period $sdram_clk_period`	`#create_clock -name {v_sdram_clk_out} -period $sdram_clk_period`