| Line 18... |
Line 18... |
set make_assignments 0
|
set make_assignments 0
|
}
|
}
|
} else {
|
} else {
|
# Only open if not already open
|
# Only open if not already open
|
if {[project_exists versatile_memory_controller]} {
|
if {[project_exists versatile_memory_controller]} {
|
project_open -revision wb_sdram_ctrl_top versatile_memory_controller
|
project_open -revision versatile_mem_ctrl_top versatile_memory_controller
|
} else {
|
} else {
|
project_new -revision wb_sdram_ctrl_top versatile_memory_controller
|
project_new -revision versatile_mem_ctrl_top versatile_memory_controller
|
}
|
}
|
set need_to_close_project 1
|
set need_to_close_project 1
|
}
|
}
|
|
|
# Make assignments
|
# Make assignments
|
| Line 44... |
Line 44... |
set_global_assignment -name SEARCH_PATH altera/90/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/
|
set_global_assignment -name SEARCH_PATH altera/90/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
set_global_assignment -name MISC_FILE /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run/wb_sdram_ctrl_top.dpf
|
set_global_assignment -name MISC_FILE /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run/versatile_mem_ctrl_top.dpf
|
set_global_assignment -name SDC_FILE ../bin/versatile_memory_controller.sdc
|
set_global_assignment -name SDC_FILE ../bin/versatile_memory_controller.sdc
|
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/versatile_mem_ctrl_ip.v
|
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/versatile_mem_ctrl_ip.v
|
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run -section_id eda_simulation
|
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run -section_id eda_simulation
|
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
|
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
