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[/] [vg_z80_sbc/] [trunk/] [rtl/] [ddr_pulse78.v] - Diff between revs 3 and 20
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///////////////////////////////////////////////////////////////////
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//----------------------------------------------------------------------------
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//
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// Wishbone DDR Controller
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// Wishbone DDR Controller
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//
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//
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// (c) Joerg Bornschein (<jb@capsec.org>)
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// (c) Joerg Bornschein (<jb@capsec.org>)
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//
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//----------------------------------------------------------------------------
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`include "ddr_include.v"
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`include "ddr_include.v"
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module ddr_pulse78 (
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module ddr_pulse78 #(
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parameter clk_freq = 50000000
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) (
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input clk,
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input clk,
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input reset,
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input reset,
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//
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//
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output pulse78
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output reg pulse78
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);
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);
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`define PULSE78_RNG 8:0
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//----------------------------------------------------------------------------
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`define PULSE78_INIT 389
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//
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//----------------------------------------------------------------------------
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`define PULSE78_RNG 10:0
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reg [`PULSE78_RNG] counter;
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parameter pulse78_init = 78 * (clk_freq/10000000);
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reg pulse78_reg;
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assign pulse78 = pulse78_reg;
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reg [`PULSE78_RNG] counter;
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset) begin
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if (reset) begin
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counter <= `PULSE78_INIT;
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counter <= pulse78_init;
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pulse78_reg <= 0;
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pulse78 <= 0;
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end else begin
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end else begin
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if (counter == 0) begin
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if (counter == 0) begin
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counter <= `PULSE78_INIT;
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counter <= pulse78_init;
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pulse78_reg <= 1'b1;
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pulse78 <= 1'b1;
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end else begin
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end else begin
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counter <= counter - 1;
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counter <= counter - 1;
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pulse78_reg <= 0;
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pulse78 <= 0;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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// vim: set ts=4
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No newline at end of file
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