URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [vg_z80_sbc.defines] - Diff between revs 3 and 10

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Rev 3	Rev 10
Line 1...	Line 1...
`# Generated by PERL program wishbone.pl.`	`# Generated by PERL program wishbone.pl.`
`# File used as input for wishbone arbiter generation`	`# File used as input for wishbone arbiter generation`
`# Generated Wed Nov 26 14:33:45 2008`	`# Generated Sun Dec 7 17:41:47 2008`

`filename=wb`	`filename=wb`
`intercon=intercon`	`intercon=intercon`
`syscon=syscon`	`syscon=syscon`
`target=generic`	`target=generic`
Line 35...	Line 35...
`priority_wbs_ddr=4`	`priority_wbs_ddr=4`
`priority_wbs_mmu=5`	`priority_wbs_mmu=5`
`priority_wbs_vga=6`	`priority_wbs_vga=6`
`priority_wb_uart0=7`	`priority_wb_uart0=7`
`priority_wb_uart1=8`	`priority_wb_uart1=8`
	`priority_wbs_vhdfd=9`
	`priority_wbs_spimaster=10`
	`priority_wbs_fpb=11`
`end master wb32_pci_master`	`end master wb32_pci_master`

`master wbm_z80`	`master wbm_z80`
`type=rw`	`type=rw`
`lock_o=0`	`lock_o=0`
Line 53...	Line 56...
`priority_wbs_ddr=4`	`priority_wbs_ddr=4`
`priority_wbs_mmu=5`	`priority_wbs_mmu=5`
`priority_wbs_vga=6`	`priority_wbs_vga=6`
`priority_wb_uart0=7`	`priority_wb_uart0=7`
`priority_wb_uart1=8`	`priority_wb_uart1=8`
	`priority_wbs_vhdfd=9`
	`priority_wbs_spimaster=10`
	`priority_wbs_fpb=11`
`end master wbm_z80`	`end master wbm_z80`

`slave wb_cpu_ctrl`	`slave wb_cpu_ctrl`
`type=rw`	`type=rw`
`adr_i_hi=7`	`adr_i_hi=2`
`adr_i_lo=2`	`adr_i_lo=0`
`tga_i=0`	`tga_i=0`
`tgc_i=0`	`tgc_i=0`
`tgd_i=0`	`tgd_i=0`
`lock_i=0`	`lock_i=0`
`err_o=0`	`err_o=0`
`rty_o=0`	`rty_o=0`
`baseadr=0x200`	`baseadr=0x40`
`size=0x100`	`size=0x20`
`baseadr1=0x00000000`	`baseadr1=0x00000000`
`size1=0xffffffff`	`size1=0xffffffff`
`baseadr2=0x00000000`	`baseadr2=0x00000000`
`size2=0xffffffff`	`size2=0xffffffff`
`end slave wb_cpu_ctrl`	`end slave wb_cpu_ctrl`
Line 129...	Line 135...
`size2=0xffffffff`	`size2=0xffffffff`
`end slave wbs_ddr`	`end slave wbs_ddr`

`slave wbs_mmu`	`slave wbs_mmu`
`type=rw`	`type=rw`
`adr_i_hi=9`	`adr_i_hi=1`
`adr_i_lo=0`	`adr_i_lo=0`
`tga_i=0`	`tga_i=0`
`tgc_i=0`	`tgc_i=0`
`tgd_i=0`	`tgd_i=0`
`lock_i=0`	`lock_i=0`
`err_o=0`	`err_o=0`
`rty_o=0`	`rty_o=0`
`baseadr=0xF00000`	`baseadr=0x60`
`size=0x100000`	`size=0x20`
`baseadr1=0x00000000`	`baseadr1=0x00000000`
`size1=0xffffffff`	`size1=0xffffffff`
`baseadr2=0x00000000`	`baseadr2=0x00000000`
`size2=0xffffffff`	`size2=0xffffffff`
`end slave wbs_mmu`	`end slave wbs_mmu`
Line 165...	Line 171...
`size2=0xffffffff`	`size2=0xffffffff`
`end slave wbs_vga`	`end slave wbs_vga`

`slave wb_uart0`	`slave wb_uart0`
`type=rw`	`type=rw`
`adr_i_hi=4`	`adr_i_hi=2`
`adr_i_lo=2`	`adr_i_lo=0`
`tga_i=0`	`tga_i=0`
`tgc_i=0`	`tgc_i=0`
`tgd_i=0`	`tgd_i=0`
`lock_i=0`	`lock_i=0`
`err_o=0`	`err_o=0`
`rty_o=0`	`rty_o=0`
`baseadr=0xE0`	`baseadr=0x20`
`size=0x20`	`size=0x20`
`baseadr1=0x00000000`	`baseadr1=0x00000000`
`size1=0xffffffff`	`size1=0xffffffff`
`baseadr2=0x00000000`	`baseadr2=0x00000000`
`size2=0xffffffff`	`size2=0xffffffff`
Line 198...	Line 204...
`baseadr1=0x00000000`	`baseadr1=0x00000000`
`size1=0xffffffff`	`size1=0xffffffff`
`baseadr2=0x00000000`	`baseadr2=0x00000000`
`size2=0xffffffff`	`size2=0xffffffff`
`end slave wb_uart1`	`end slave wb_uart1`

	`slave wbs_vhdfd`
	`type=rw`
	`adr_i_hi=2`
	`adr_i_lo=0`
	`tga_i=0`
	`tgc_i=0`
	`tgd_i=0`
	`lock_i=0`
	`err_o=0`
	`rty_o=0`
	`baseadr=0xc0`
	`size=0x20`
	`baseadr1=0x00000000`
	`size1=0xffffffff`
	`baseadr2=0x00000000`
	`size2=0xffffffff`
	`end slave wbs_vhdfd`

	`slave wbs_spimaster`
	`type=rw`
	`adr_i_hi=5`
	`adr_i_lo=0`
	`tga_i=0`
	`tgc_i=0`
	`tgd_i=0`
	`lock_i=0`
	`err_o=0`
	`rty_o=0`
	`baseadr=0x80`
	`size=0x40`
	`baseadr1=0x00000000`
	`size1=0xffffffff`
	`baseadr2=0x00000000`
	`size2=0xffffffff`
	`end slave wbs_spimaster`

	`slave wbs_fpb`
	`type=rw`
	`adr_i_hi=4`
	`adr_i_lo=0`
	`tga_i=0`
	`tgc_i=0`
	`tgd_i=0`
	`lock_i=0`
	`err_o=0`
	`rty_o=0`
	`baseadr=0xe0`
	`size=0x20`
	`baseadr1=0x00000000`
	`size1=0xffffffff`
	`baseadr2=0x00000000`
	`size2=0xffffffff`
	`end slave wbs_fpb`

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[/] [vg_z80_sbc/] [trunk/] [rtl/] [vg_z80_sbc.defines] - Diff between revs 3 and 10