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URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [vg_z80_sbc.defines] - Diff between revs 10 and 30

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Rev 10 Rev 30
Line 1... Line 1...
# Generated by PERL program wishbone.pl.
# Generated by PERL program wishbone.pl.
# File used as input for wishbone arbiter generation
# File used as input for wishbone arbiter generation
# Generated Sun Dec  7 17:41:47 2008
# Generated Mon Dec  8 20:57:48 2008
 
 
filename=wb
filename=wb
intercon=intercon
intercon=intercon
syscon=syscon
syscon=syscon
target=generic
target=generic
Line 27... Line 27...
  tga_o=0
  tga_o=0
  tgc_o=0
  tgc_o=0
  tgd_o=0
  tgd_o=0
  err_i=1
  err_i=1
  rty_i=0
  rty_i=0
  priority_wb_cpu_ctrl=1
  priority_wbs_sram=1
  priority_wb_sram=2
  priority_wbs_flash=2
  priority_wbs_flash=3
  priority_wbs_ddr=3
  priority_wbs_ddr=4
  priority_wbs_vga=4
  priority_wbs_mmu=5
  priority_wbs_kbd=5
  priority_wbs_vga=6
  priority_wbs_mmu=6
  priority_wb_uart0=7
  priority_wb_cpu_ctrl=7
  priority_wb_uart1=8
  priority_wbs_spimaster=8
  priority_wbs_vhdfd=9
  priority_wbs_vhdfd=9
  priority_wbs_spimaster=10
  priority_wbs_fpb=10
  priority_wbs_fpb=11
 
end master wb32_pci_master
end master wb32_pci_master
 
 
master wbm_z80
master wbm_z80
  type=rw
  type=rw
  lock_o=0
  lock_o=0
  tga_o=0
  tga_o=0
  tgc_o=0
  tgc_o=0
  tgd_o=0
  tgd_o=0
  err_i=0
  err_i=0
  rty_i=0
  rty_i=0
  priority_wb_cpu_ctrl=1
  priority_wbs_sram=1
  priority_wb_sram=2
  priority_wbs_flash=2
  priority_wbs_flash=3
  priority_wbs_ddr=3
  priority_wbs_ddr=4
  priority_wbs_vga=4
  priority_wbs_mmu=5
  priority_wbs_kbd=5
  priority_wbs_vga=6
  priority_wbs_mmu=6
  priority_wb_uart0=7
  priority_wb_cpu_ctrl=7
  priority_wb_uart1=8
  priority_wbs_spimaster=8
  priority_wbs_vhdfd=9
  priority_wbs_vhdfd=9
  priority_wbs_spimaster=10
  priority_wbs_fpb=10
  priority_wbs_fpb=11
 
end master wbm_z80
end master wbm_z80
 
 
slave wb_cpu_ctrl
slave wbs_sram
  type=rw
 
  adr_i_hi=2
 
  adr_i_lo=0
 
  tga_i=0
 
  tgc_i=0
 
  tgd_i=0
 
  lock_i=0
 
  err_o=0
 
  rty_o=0
 
  baseadr=0x40
 
  size=0x20
 
  baseadr1=0x00000000
 
  size1=0xffffffff
 
  baseadr2=0x00000000
 
  size2=0xffffffff
 
end slave wb_cpu_ctrl
 
 
 
slave wb_sram
 
  type=rw
  type=rw
  adr_i_hi=14
  adr_i_hi=14
  adr_i_lo=0
  adr_i_lo=0
  tga_i=0
  tga_i=0
  tgc_i=0
  tgc_i=0
Line 95... Line 75...
  size=0x100000
  size=0x100000
  baseadr1=0x00000000
  baseadr1=0x00000000
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wb_sram
end slave wbs_sram
 
 
slave wbs_flash
slave wbs_flash
  type=rw
  type=rw
  adr_i_hi=18
  adr_i_hi=18
  adr_i_lo=0
  adr_i_lo=0
Line 133... Line 113...
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wbs_ddr
end slave wbs_ddr
 
 
slave wbs_mmu
slave wbs_vga
  type=rw
  type=rw
  adr_i_hi=1
  adr_i_hi=13
  adr_i_lo=0
  adr_i_lo=0
  tga_i=0
  tga_i=0
  tgc_i=0
  tgc_i=0
  tgd_i=0
  tgd_i=0
  lock_i=0
  lock_i=0
  err_o=0
  err_o=0
  rty_o=0
  rty_o=0
  baseadr=0x60
  baseadr=0x600000
  size=0x20
  size=0x100000
  baseadr1=0x00000000
  baseadr1=0x00000000
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wbs_mmu
end slave wbs_vga
 
 
slave wbs_vga
slave wbs_kbd
  type=rw
  type=rw
  adr_i_hi=13
  adr_i_hi=2
  adr_i_lo=0
  adr_i_lo=0
  tga_i=0
  tga_i=0
  tgc_i=0
  tgc_i=0
  tgd_i=0
  tgd_i=0
  lock_i=0
  lock_i=0
  err_o=0
  err_o=0
  rty_o=0
  rty_o=0
  baseadr=0x600000
  baseadr=0x00
  size=0x100000
  size=0x20
  baseadr1=0x00000000
  baseadr1=0x00000000
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wbs_vga
end slave wbs_kbd
 
 
slave wb_uart0
slave wbs_mmu
  type=rw
  type=rw
  adr_i_hi=2
  adr_i_hi=1
  adr_i_lo=0
  adr_i_lo=0
  tga_i=0
  tga_i=0
  tgc_i=0
  tgc_i=0
  tgd_i=0
  tgd_i=0
  lock_i=0
  lock_i=0
Line 185... Line 165...
  size=0x20
  size=0x20
  baseadr1=0x00000000
  baseadr1=0x00000000
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wb_uart0
end slave wbs_mmu
 
 
slave wb_uart1
slave wb_cpu_ctrl
  type=rw
  type=rw
  adr_i_hi=4
  adr_i_hi=2
  adr_i_lo=0
  adr_i_lo=0
  tga_i=0
  tga_i=0
  tgc_i=0
  tgc_i=0
  tgd_i=0
  tgd_i=0
  lock_i=0
  lock_i=0
  err_o=0
  err_o=0
  rty_o=0
  rty_o=0
  baseadr=0x00
  baseadr=0x40
  size=0x20
  size=0x40
  baseadr1=0x00000000
  baseadr1=0x00000000
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wb_uart1
end slave wb_cpu_ctrl
 
 
slave wbs_vhdfd
slave wbs_spimaster
  type=rw
  type=rw
  adr_i_hi=2
  adr_i_hi=5
  adr_i_lo=0
  adr_i_lo=0
  tga_i=0
  tga_i=0
  tgc_i=0
  tgc_i=0
  tgd_i=0
  tgd_i=0
  lock_i=0
  lock_i=0
  err_o=0
  err_o=0
  rty_o=0
  rty_o=0
  baseadr=0xc0
  baseadr=0x80
  size=0x20
  size=0x40
  baseadr1=0x00000000
  baseadr1=0x00000000
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wbs_vhdfd
end slave wbs_spimaster
 
 
slave wbs_spimaster
slave wbs_vhdfd
  type=rw
  type=rw
  adr_i_hi=5
  adr_i_hi=2
  adr_i_lo=0
  adr_i_lo=0
  tga_i=0
  tga_i=0
  tgc_i=0
  tgc_i=0
  tgd_i=0
  tgd_i=0
  lock_i=0
  lock_i=0
  err_o=0
  err_o=0
  rty_o=0
  rty_o=0
  baseadr=0x80
  baseadr=0xc0
  size=0x40
  size=0x20
  baseadr1=0x00000000
  baseadr1=0x00000000
  size1=0xffffffff
  size1=0xffffffff
  baseadr2=0x00000000
  baseadr2=0x00000000
  size2=0xffffffff
  size2=0xffffffff
end slave wbs_spimaster
end slave wbs_vhdfd
 
 
slave wbs_fpb
slave wbs_fpb
  type=rw
  type=rw
  adr_i_hi=4
  adr_i_hi=4
  adr_i_lo=0
  adr_i_lo=0

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