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Line 6... |
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`include "ddr_include.v"
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`include "ddr_include.v"
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module wb_ddr
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module wb_ddr
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#(
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#(
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parameter phase_shift = 0,
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parameter clk_freq = 100000000,
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parameter clk_multiply = 12,
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parameter clk_multiply = 12,
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parameter clk_divide = 5,
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parameter clk_divide = 5,
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parameter phase_shift = 0,
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parameter wait200_init = 26
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parameter wait200_init = 26
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) (
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) (
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input clk,
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input clk,
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input reset,
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input reset,
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// XXX -- DCM phase control -- XXX
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input [2:0] rot,
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// DDR ports
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// DDR ports
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output ddr_clk,
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output [2:0] ddr_clk,
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output ddr_clk_n,
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output [2:0] ddr_clk_n,
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input ddr_clk_fb,
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input ddr_clk_fb,
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output ddr_ras_n,
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output ddr_ras_n,
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output ddr_cas_n,
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output ddr_cas_n,
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output ddr_we_n,
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output ddr_we_n,
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output ddr_cke,
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output [1:0] ddr_cke,
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output ddr_cs_n,
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output [1:0] ddr_cs_n,
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output [ `A_RNG] ddr_a,
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output [ `A_RNG] ddr_a,
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output [ `BA_RNG] ddr_ba,
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output [ `BA_RNG] ddr_ba,
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inout [ `DQ_RNG] ddr_dq,
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inout [ `DQ_RNG] ddr_dq,
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inout [`DQS_RNG] ddr_dqs,
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inout [`DQS_RNG] ddr_dqs,
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output [ `DM_RNG] ddr_dm,
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output [ `DM_RNG] ddr_dm,
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output reg [`WB_DAT_RNG] wb_dat_o,
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output reg [`WB_DAT_RNG] wb_dat_o,
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input [`WB_SEL_RNG] wb_sel_i,
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input [`WB_SEL_RNG] wb_sel_i,
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input wb_cyc_i,
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input wb_cyc_i,
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input wb_stb_i,
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input wb_stb_i,
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input wb_we_i,
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input wb_we_i,
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output reg wb_ack_o
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output reg wb_ack_o,
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// XXX Temporary DCM control input XXX
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output ps_ready,
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input ps_up,
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input ps_down,
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// XXX probe wires XXX
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output probe_clk,
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input [7:0] probe_sel,
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output reg [7:0] probe
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);
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);
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Wishbone handling
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// Wishbone handling
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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Line 448... |
.clk_divide( clk_divide ),
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.clk_divide( clk_divide ),
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.wait200_init( wait200_init )
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.wait200_init( wait200_init )
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) ctrl0 (
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) ctrl0 (
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.clk( clk ),
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.clk( clk ),
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.reset( reset ),
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.reset( reset ),
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.rot( rot ),
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// DDR Ports
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// DDR Ports
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.ddr_clk( ddr_clk ),
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.ddr_clk( ddr_clk ),
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.ddr_clk_n( ddr_clk_n ),
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.ddr_clk_n( ddr_clk_n ),
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.ddr_clk_fb( ddr_clk_fb ),
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.ddr_clk_fb( ddr_clk_fb ),
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.ddr_ras_n( ddr_ras_n ),
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.ddr_ras_n( ddr_ras_n ),
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Line 472... |
.fml_wdat( fml_wdat ),
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.fml_wdat( fml_wdat ),
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.fml_wbe( fml_wbe ),
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.fml_wbe( fml_wbe ),
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.fml_wnext( fml_wnext2 ),
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.fml_wnext( fml_wnext2 ),
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.fml_rempty( fml_rempty ),
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.fml_rempty( fml_rempty ),
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.fml_rdat( fml_rdat ),
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.fml_rdat( fml_rdat ),
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.fml_rnext( fml_rnext )
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.fml_rnext( fml_rnext ),
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// DCM phase shift control
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.ps_ready( ps_ready ),
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.ps_up( ps_up ),
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.ps_down( ps_down )
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);
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);
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assign fml_adr = { ls_adr_tag, ls_adr_set };
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assign fml_adr = { ls_adr_tag, ls_adr_set };
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assign fml_wdat = (ls_way) ? ls_way1_load[`WAY_DAT_RNG] :
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assign fml_wdat = (ls_way) ? ls_way1_load[`WAY_DAT_RNG] :
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Line 616... |
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if (ls_spill)
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if (ls_spill)
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$display ("At time %t WB_DDR spill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);
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$display ("At time %t WB_DDR spill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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