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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: wb_sram.v,v 1.3 2008-12-08 06:55:36 hharte Exp $ ////
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//// $Id: wb_sram.v,v 1.4 2008-12-13 21:04:13 hharte Exp $ ////
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//// wb_sram.v - SRAM with Wishbone Slave interface. ////
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//// wb_sram.v - SRAM with Wishbone Slave interface. ////
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//// ////
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//// ////
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//// This file is part of the Vector Graphic Z80 SBC Project ////
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//// This file is part of the Vector Graphic Z80 SBC Project ////
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//// http://www.opencores.org/projects/vg_z80_sbc/ ////
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//// http://www.opencores.org/projects/vg_z80_sbc/ ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module wb_sram
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module wb_sram
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#(
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#(
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parameter mem_file_name = "none",
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parameter mem_file_name = "none",
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parameter adr_width = 14,
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parameter adr_width = 14,
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parameter dat_width = 8
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parameter dat_width = 8,
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parameter dw = 32 //number of data-bits
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) (
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) (
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
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clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
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wb_stb_i, wb_cyc_i, wb_ack_o
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wb_stb_i, wb_cyc_i, wb_ack_o
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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//
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//
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parameter aw = 15; //number of address-bits
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parameter dw = 32; //number of data-bits
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk_i;
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input clk_i;
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input nrst_i;
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input nrst_i;
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input [aw-1:0] wb_adr_i;
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input [adr_width-1:0] wb_adr_i;
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output [dw-1:0] wb_dat_o;
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output [dw-1:0] wb_dat_o;
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input [dw-1:0] wb_dat_i;
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input [dw-1:0] wb_dat_i;
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input [3:0] wb_sel_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_stb_i;
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