URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [tests.v] - Diff between revs 29 and 38

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 29	Rev 38
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: tests.v,v 1.4 2002-02-07 05:38:32 rherveille Exp $`	`// $Id: tests.v,v 1.5 2002-04-20 09:57:55 rherveille Exp $`
`//`	`//`
`// $Date: 2002-02-07 05:38:32 $`	`// $Date: 2002-04-20 09:57:55 $`
`// $Revision: 1.4 $`	`// $Revision: 1.5 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
Line 513...	Line 513...

`$display("VBL: %0d, Mode: %0d", vbl, mode);`	`$display("VBL: %0d, Mode: %0d", vbl, mode);`
`repeat(2) @(posedge vsync);`	`repeat(2) @(posedge vsync);`

`// For Each Line`	`// For Each Line`
`for(l=0;l<tvgate+1;l=l+1)`	`for(l=0;l<tvgate;l=l+1)`
`// For each Pixel`	`// For each Pixel`
`for(p=0;p<thgate+1;p=p+1)`	`for(p=0;p<thgate+1;p=p+1)`
`begin`	`begin`
`while(blanc) @(posedge pclk); // wait for viewable data`	`while(blanc) @(posedge pclk); // wait for viewable data`

Line 705...	Line 705...
`thgate = 319;`	`thgate = 319;`
`thlen = 390;`	`thlen = 390;`

`tvsync = 1;`	`tvsync = 1;`
`tvgdel = 8;`	`tvgdel = 8;`
`tvgate = 239;`	`// tvgate = 239;`
	`tvgate = 240;`
`tvlen = 280;`	`tvlen = 280;`

`/*`	`/*`
`thsync = 0;`	`thsync = 0;`
`thgdel = 0;`	`thgdel = 0;`
Line 757...	Line 758...
`repeat(10) @(posedge clk);`	`repeat(10) @(posedge clk);`
`endif	`endif


`vbl = 0;`	`vbl = 0;`
`mode = 2;`	`mode = 1;`

`for(vbl=0;vbl<4;vbl=vbl+1)`	`for(vbl=0;vbl<4;vbl=vbl+1)`
`for(mode=0;mode<=4;mode=mode+1)`	`for(mode=0;mode<=4;mode=mode+1)`
`begin`	`begin`

Line 826...	Line 827...
`$display("VBL: %0d, Mode: %0d Screen: %0d", vbl, mode, bank);`	`$display("VBL: %0d, Mode: %0d Screen: %0d", vbl, mode, bank);`
`@(posedge vsync);`	`@(posedge vsync);`

`error_cnt=0;`	`error_cnt=0;`
`// For Each Line`	`// For Each Line`
`for(l=0;l<tvgate+1;l=l+1)`	`// for(l=0;l<tvgate+1;l=l+1)`
	`for(l=0; l<tvgate;l=l+1)`
`// For each Pixel`	`// For each Pixel`
`for(p=0;p<thgate+1;p=p+1)`	`for(p=0;p<thgate+1;p=p+1)`
`begin`	`begin`
`while(blanc) @(posedge pclk); // wait for viewable data`	`while(blanc) @(posedge pclk); // wait for viewable data`

Line 1183...	Line 1185...

Browse

Tools

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [tests.v] - Diff between revs 29 and 38