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Rev 16	Rev 29
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`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: wb_slv_model.v,v 1.1 2001-08-21 05:42:32 rudi Exp $`	`// $Id: wb_slv_model.v,v 1.2 2002-02-07 05:38:32 rherveille Exp $`
`//`	`//`
`// $Date: 2001-08-21 05:42:32 $`	`// $Date: 2002-02-07 05:38:32 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/08/21 05:42:32 rudi`
	`//`
	`// - Changed Directory Structure`
	`// - Added verilog Source Code`
	`// - Changed IO pin names and defines statements`
	`//`
`//`	`//`
`//`	`//`
`//`	`//`

`include "wb_model_defines.v"	`include "wb_model_defines.v"
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`always @(posedge clk)`	`always @(posedge clk)`
`if(mem_we) mem[adr[mem_size+1:2]] <= #1 tmp2;`	`if(mem_we) mem[adr[mem_size+1:2]] <= #1 tmp2;`

`always @(posedge clk)`	`always @(posedge clk)`
`del_ack = ack ? 0 : {del_ack[30:0], (mem_re \| mem_we)};`	`del_ack = ack ? 0 : {del_ack[30:0], cyc & stb};`

`assign #3 ack = cyc & ((delay==0) ? (mem_re \| mem_we) : del_ack[delay-1]);`	`assign ack = cyc & stb & ((delay==0) ? 1'b1 : del_ack[delay-1]);`

`task fill_mem;`	`task fill_mem;`
`input mode;`	`input mode;`

`integer n, mode;`	`integer n, mode;`
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`end`	`end`
`endtask`	`endtask`

`endmodule`	`endmodule`

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`No newline at end of file`	`No newline at end of file`

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////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: wb_slv_model.v,v 1.1 2001-08-21 05:42:32 rudi Exp $

//  $Id: wb_slv_model.v,v 1.2 2002-02-07 05:38:32 rherveille Exp $

//

//

//  $Date: 2001-08-21 05:42:32 $

//  $Date: 2002-02-07 05:38:32 $

//  $Revision: 1.1 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Author: rherveille $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.1  2001/08/21 05:42:32  rudi

//

//               - Changed Directory Structure

//               - Added verilog Source Code

//               - Changed IO pin names and defines statements

//

//

//

//

//

//

//

`include "wb_model_defines.v"

`include "wb_model_defines.v"

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always @(posedge clk)

always @(posedge clk)

        if(mem_we)      mem[adr[mem_size+1:2]] <= #1 tmp2;

        if(mem_we)      mem[adr[mem_size+1:2]] <= #1 tmp2;

always @(posedge clk)

always @(posedge clk)

        del_ack = ack ? 0 : {del_ack[30:0], (mem_re | mem_we)};

        del_ack = ack ? 0 : {del_ack[30:0], cyc & stb};

assign  #3 ack = cyc & ((delay==0) ? (mem_re | mem_we) : del_ack[delay-1]);

assign  ack = cyc & stb & ((delay==0) ? 1'b1 : del_ack[delay-1]);

task fill_mem;

task fill_mem;

input           mode;

input           mode;

integer         n, mode;

integer         n, mode;

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end

end

endtask

endtask

endmodule

endmodule

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