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//
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//
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// File colproc.vhd, Color Processor
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// File colproc.vhd, Color Processor
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// Project: VGA
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// Project: VGA
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// Author : Richard Herveille. Ideas and thoughts: Sherif Taher Eid
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// Author : Richard Herveille. Ideas and thoughts: Sherif Taher Eid
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//
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// rev. 1.0 August 2nd, 2001. Initial Verilog release
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// rev. 1.0 August 2nd, 2001. Initial Verilog release
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// rev. 1.1 August 29th, 2001. Changed statemachine to increase bandwidth.
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// rev. 1.1 August 29th, 2001. Changed statemachine to increase bandwidth.
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//
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// rev. 2.0 October 2nd, 2001. Revised core. Included color lookup table in Color Processor
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`include "timescale.v"
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`include "timescale.v"
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module vga_colproc(clk, srst, pixel_buffer_di, wb_di, ColorDepth, PseudoColor,
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module vga_colproc(clk, srst, pixel_buffer_di, ColorDepth, PseudoColor,
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pixel_buffer_empty, pixel_buffer_rreq, RGB_fifo_full,
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pixel_buffer_empty, pixel_buffer_rreq, RGB_fifo_full,
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RGB_fifo_wreq, R, G, B, clut_req, clut_offs, clut_ack);
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RGB_fifo_wreq, R, G, B,
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clut_req, clut_ack, clut_offs, clut_q);
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//
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// inputs & outputs
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// inputs & outputs
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//
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input clk; // master clock
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input clk; // master clock
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input srst; // synchronous reset
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input srst; // synchronous reset
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input [31:0] pixel_buffer_di; // Pixel Buffer data input
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input [31:0] pixel_buffer_di; // Pixel Buffer data input
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input [31:0] wb_di; // wishbone data input
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input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)
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input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)
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input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
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input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
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input pixel_buffer_empty;
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input pixel_buffer_empty;
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output RGB_fifo_wreq;
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output RGB_fifo_wreq;
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reg RGB_fifo_wreq;
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reg RGB_fifo_wreq;
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output [7:0] R, G, B; // pixel color information
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output [7:0] R, G, B; // pixel color information
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reg [7:0] R, G, B;
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reg [7:0] R, G, B;
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output clut_req; // Color lookup table access request
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output clut_req; // clut request
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reg clut_req;
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reg clut_req;
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output [7:0] clut_offs; // offset into color lookup table
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input clut_ack; // clut acknowledge
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output [ 7:0] clut_offs; // clut offset
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reg [7:0] clut_offs;
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reg [7:0] clut_offs;
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input clut_ack; // Color lookup table data acknowledge
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input [23:0] clut_q; // clut data in
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//
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// variable declarations
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// variable declarations
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//
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reg [31:0] DataBuffer;
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reg [31:0] DataBuffer;
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reg [7:0] Ra, Ga, Ba;
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reg [7:0] Ra, Ga, Ba;
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reg [1:0] colcnt;
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reg [1:0] colcnt;
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reg RGBbuf_wreq;
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reg RGBbuf_wreq;
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//
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//
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// Module body
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// Module body
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//
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//
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// store word from pixelbuffer / wishbone input
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// store word from pixelbuffer / wishbone input
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c_state <= #1 idle;
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c_state <= #1 idle;
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else
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else
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c_state <= #1 nxt_state;
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c_state <= #1 nxt_state;
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reg clut_acc;
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reg iclut_req;
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reg pixelbuf_rreq;
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reg pixelbuf_rreq;
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reg [7:0] iR, iG, iB, iRa, iGa, iBa;
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reg [7:0] iR, iG, iB, iRa, iGa, iBa;
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// output decoder
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// output decoder
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always@(c_state or pixel_buffer_empty or colcnt or DataBuffer or RGB_fifo_full or clut_ack or wb_di or Ba or Ga or Ra)
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always@(c_state or pixel_buffer_empty or colcnt or DataBuffer or RGB_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)
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begin : output_decoder
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begin : output_decoder
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// initial values
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// initial values
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pixelbuf_rreq = 1'b0;
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pixelbuf_rreq = 1'b0;
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RGBbuf_wreq = 1'b0;
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RGBbuf_wreq = 1'b0;
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clut_acc = 1'b0;
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iclut_req = 1'b0;
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iR = 'h0;
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iR = 'h0;
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iG = 'h0;
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iG = 'h0;
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iB = 'h0;
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iB = 'h0;
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iRa = 'h0;
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iRa = 'h0;
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if ( (!pixel_buffer_empty) && !(|colcnt) )
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if ( (!pixel_buffer_empty) && !(|colcnt) )
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pixelbuf_rreq = 1'b1;
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pixelbuf_rreq = 1'b1;
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end
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end
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iR = wb_di[23:16];
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iR = clut_q[23:16];
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iG = wb_di[15: 8];
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iG = clut_q[15: 8];
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iB = wb_di[ 7: 0];
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iB = clut_q[ 7: 0];
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clut_acc = ~RGB_fifo_full;
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iclut_req = ~RGB_fifo_full;
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if ( !(|colcnt) && clut_ack)
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if ( !(|colcnt) && clut_ack)
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clut_acc =1'b0;
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iclut_req =1'b0;
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end
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end
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//
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//
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// 16 bits per pixel
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// 16 bits per pixel
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//
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//
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end
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end
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else
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else
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begin
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begin
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pixel_buffer_rreq <= #1 pixelbuf_rreq;
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pixel_buffer_rreq <= #1 pixelbuf_rreq;
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RGB_fifo_wreq <= #1 RGBbuf_wreq;
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RGB_fifo_wreq <= #1 RGBbuf_wreq;
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clut_req <= #1 clut_acc;
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clut_req <= #1 iclut_req;
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end
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end
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end
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end
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// assign clut offset
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// assign clut offset
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always@(colcnt or DataBuffer)
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always@(colcnt or DataBuffer)
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always@(posedge clk)
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always@(posedge clk)
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if(srst)
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if(srst)
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colcnt <= #1 2'b11;
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colcnt <= #1 2'b11;
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else if (RGBbuf_wreq)
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else if (RGBbuf_wreq)
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colcnt <= #1 colcnt -2'h1;
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colcnt <= #1 colcnt -2'h1;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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