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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_colproc.v] - Diff between revs 23 and 28

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Rev 23	Rev 28
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: vga_colproc.v,v 1.4 2001-11-14 11:45:25 rherveille Exp $`	`// $Id: vga_colproc.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $`
`//`	`//`
`// $Date: 2001-11-14 11:45:25 $`	`// $Date: 2002-01-28 03:47:16 $`
`// $Revision: 1.4 $`	`// $Revision: 1.5 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
Line 103...	Line 103...

`//`	`//`
`// generate statemachine`	`// generate statemachine`
`//`	`//`
`// extract color information from data buffer`	`// extract color information from data buffer`
`parameter idle = 6'b00_0000,`	`parameter idle = 7'b000_0000,`
`fill_buf = 6'b00_0001,`	`fill_buf = 7'b000_0001,`
`bw_8bpp = 6'b00_0010,`	`bw_8bpp = 7'b000_0010,`
`col_8bpp = 6'b00_0100,`	`col_8bpp = 7'b000_0100,`
`col_16bpp_a = 6'b00_1000,`	`col_16bpp_a = 7'b000_1000,`
`col_16bpp_b = 6'b01_0000,`	`col_16bpp_b = 7'b001_0000,`
`col_24bpp = 6'b10_0000;`	`col_24bpp = 7'b010_0000,`
	`col_32bpp = 7'b100_0000;`

`reg [5:0] c_state; // synopsis enum_state`	`reg [6:0] c_state; // synopsys enum_state`
`reg [5:0] nxt_state; // synopsis enum_state`	`reg [6:0] nxt_state; // synopsys enum_state`

`// next state decoder`	`// next state decoder`
`always@(c_state or pixel_buffer_empty or ColorDepth or PseudoColor or RGB_fifo_full or colcnt or clut_ack)`	`always@(c_state or pixel_buffer_empty or ColorDepth or PseudoColor or RGB_fifo_full or colcnt or clut_ack)`
`begin : nxt_state_decoder`	`begin : nxt_state_decoder`
`// initial value`	`// initial value`
Line 138...	Line 139...
`nxt_state = bw_8bpp;`	`nxt_state = bw_8bpp;`

`2'b01:`	`2'b01:`
`nxt_state = col_16bpp_a;`	`nxt_state = col_16bpp_a;`

`default:`	`2'b10:`
`nxt_state = col_24bpp;`	`nxt_state = col_24bpp;`

	`2'b11:`
	`nxt_state = col_32bpp;`

`endcase`	`endcase`

`//`	`//`
`// 8 bits per pixel`	`// 8 bits per pixel`
`//`	`//`
Line 187...	Line 191...
`else if (!pixel_buffer_empty)`	`else if (!pixel_buffer_empty)`
`nxt_state = fill_buf;`	`nxt_state = fill_buf;`
`else`	`else`
`nxt_state = idle;`	`nxt_state = idle;`

	`//`
	`// 32 bits per pixel`
	`//`
	`col_32bpp:`
	`if (!RGB_fifo_full)`
	`if (!pixel_buffer_empty)`
	`nxt_state = fill_buf;`
	`else`
	`nxt_state = idle;`
`endcase`	`endcase`
`end // next state decoder`	`end // next state decoder`

`// generate state registers`	`// generate state registers`
`always@(posedge clk)`	`always@(posedge clk)`
Line 366...	Line 379...
`iB = Ba;`	`iB = Ba;`
`end`	`end`
`endcase`	`endcase`
`end`	`end`

	`//`
	`// 32 bits per pixel`
	`//`
	`col_32bpp:`
	`begin`
	`if (!RGB_fifo_full)`
	`begin`
	`RGBbuf_wreq = 1'b1;`

	`if (!pixel_buffer_empty)`
	`pixelbuf_rreq = 1'b1;`
	`end`

	`iR[7:0] = DataBuffer[23:16];`
	`iG[7:0] = DataBuffer[15:8];`
	`iB[7:0] = DataBuffer[7:0];`
	`end`

`endcase`	`endcase`
`end // output decoder`	`end // output decoder`

`// generate output registers`	`// generate output registers`
`always@(posedge clk)`	`always@(posedge clk)`
Line 417...	Line 448...
`colcnt <= #1 2'b11;`	`colcnt <= #1 2'b11;`
`else if (RGBbuf_wreq)`	`else if (RGBbuf_wreq)`
`colcnt <= #1 colcnt -2'h1;`	`colcnt <= #1 colcnt -2'h1;`
`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`


`No newline at end of file`	`No newline at end of file`

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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_colproc.v] - Diff between revs 23 and 28