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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_enh_top.v,v 1.2 2002-03-04 11:01:59 rherveille Exp $
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// $Id: vga_enh_top.v,v 1.3 2003-03-18 21:45:48 rherveille Exp $
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//
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//
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// $Date: 2002-03-04 11:01:59 $
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// $Date: 2003-03-18 21:45:48 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/03/04 11:01:59 rherveille
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// Added 64x64pixels 4bpp hardware cursor support.
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//
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// Revision 1.1 2002/02/07 05:42:10 rherveille
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// Revision 1.1 2002/02/07 05:42:10 rherveille
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// Fixed some bugs discovered by modified testbench
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// Fixed some bugs discovered by modified testbench
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// Removed / Changed some strange logic constructions
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// Removed / Changed some strange logic constructions
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// Started work on hardware cursor support (not finished yet)
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// Started work on hardware cursor support (not finished yet)
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// Changed top-level name to vga_enh_top.v
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// Changed top-level name to vga_enh_top.v
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`include "timescale.v"
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`include "timescale.v"
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`include "vga_defines.v"
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`include "vga_defines.v"
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module vga_enh_top (wb_clk_i, wb_rst_i, rst_i, wb_inta_o,
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module vga_enh_top (wb_clk_i, wb_rst_i, rst_i, wb_inta_o,
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wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o,
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wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o,
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wbm_adr_o, wbm_dat_i, wbm_cab_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i,
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wbm_adr_o, wbm_dat_i, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i,
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clk_p_i, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o);
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clk_p_i, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o
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);
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//
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//
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// parameters
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// parameters
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//
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//
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parameter ARST_LVL = 1'b0;
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parameter ARST_LVL = 1'b0;
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input [31:0] wbm_dat_i; // Master databus input
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input [31:0] wbm_dat_i; // Master databus input
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output [ 3:0] wbm_sel_o; // byte select outputs
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output [ 3:0] wbm_sel_o; // byte select outputs
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output wbm_we_o; // write enable output
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output wbm_we_o; // write enable output
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output wbm_stb_o; // strobe output
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output wbm_stb_o; // strobe output
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output wbm_cyc_o; // valid bus cycle output
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output wbm_cyc_o; // valid bus cycle output
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output wbm_cab_o; // continuos address burst output
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output [ 3:0] wbm_cti_o; // cycle type identifier
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output [ 1:0] wbm_bte_o; // burst type extensions
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input wbm_ack_i; // bus cycle acknowledge input
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input wbm_ack_i; // bus cycle acknowledge input
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input wbm_err_i; // bus cycle error input
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input wbm_err_i; // bus cycle error input
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// VGA signals
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// VGA signals
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input clk_p_i; // pixel clock
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input clk_p_i; // pixel clock
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// from pixel generator
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// from pixel generator
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wire cgate; // composite gate signal
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wire cgate; // composite gate signal
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wire ihsync, ivsync, icsync, iblank; // intermediate horizontal/vertical/composite sync, intermediate blank
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wire ihsync, ivsync, icsync, iblank; // intermediate horizontal/vertical/composite sync, intermediate blank
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// line fifo connections
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// line fifo connections
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wire line_fifo_dpm_wreq;
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wire line_fifo_dpm_wreq, line_fifo_empty_rd;
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wire [23:0] line_fifo_dpm_d, line_fifo_dpm_q;
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wire [23:0] line_fifo_dpm_d, line_fifo_dpm_q;
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// clut connections
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// clut connections
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wire ext_clut_req, ext_clut_ack;
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wire ext_clut_req, ext_clut_ack;
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wire [23:0] ext_clut_q;
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wire [23:0] ext_clut_q;
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//
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//
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// Module body
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// Module body
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//
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//
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// hookup wishbone slave
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// hookup wishbone slave
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vga_wb_slave u1 (
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vga_wb_slave wbs (
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// wishbone interface
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// wishbone interface
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.clk_i(wb_clk_i),
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.clk_i(wb_clk_i),
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.rst_i(wb_rst_i),
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.rst_i(wb_rst_i),
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.arst_i(arst),
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.arst_i(arst),
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.adr_i(wbs_adr_i[11:2]),
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.adr_i(wbs_adr_i[11:2]),
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.clut_ack(ext_clut_ack),
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.clut_ack(ext_clut_ack),
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.clut_q(ext_clut_q)
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.clut_q(ext_clut_q)
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);
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);
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// hookup wishbone master
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// hookup wishbone master
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vga_wb_master u2 (
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vga_wb_master wbm (
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// wishbone interface
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// wishbone interface
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.clk_i(wb_clk_i),
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.clk_i(wb_clk_i),
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.rst_i(wb_rst_i),
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.rst_i(wb_rst_i),
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.nrst_i(arst),
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.nrst_i(arst),
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.cyc_o(wbm_cyc_o),
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.cyc_o(wbm_cyc_o),
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.stb_o(wbm_stb_o),
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.stb_o(wbm_stb_o),
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.cab_o(wbm_cab_o),
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.cti_o(wbm_cti_o),
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.bte_o(wbm_bte_o),
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.we_o(wbm_we_o),
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.we_o(wbm_we_o),
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.adr_o(wbm_adr_o),
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.adr_o(wbm_adr_o),
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.sel_o(wbm_sel_o),
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.sel_o(wbm_sel_o),
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.ack_i(wbm_ack_i),
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.ack_i(wbm_ack_i),
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.err_i(wbm_err_i),
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.err_i(wbm_err_i),
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.dat1_o(ext_clut_q),
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.dat1_o(ext_clut_q),
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.we1_i(wbs_we_i)
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.we1_i(wbs_we_i)
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);
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);
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// hookup pixel and video timing generator
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// hookup pixel and video timing generator
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vga_pgen u3 (
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vga_pgen pixel_generator (
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.mclk(wb_clk_i),
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.mclk(wb_clk_i),
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.pclk(clk_p_i),
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.pclk(clk_p_i),
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.ctrl_ven(ctrl_ven),
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.ctrl_ven(ctrl_ven),
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.ctrl_HSyncL(ctrl_hsl),
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.ctrl_HSyncL(ctrl_hsl),
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.Thsync(Thsync),
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.Thsync(Thsync),
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Line 342... |
csync_pad_o <= #1 icsync;
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csync_pad_o <= #1 icsync;
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blank_pad_o <= #1 iblank;
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blank_pad_o <= #1 iblank;
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end
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end
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// hookup line-fifo
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// hookup line-fifo
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vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) u4 (
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vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) line_fifo (
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.rclk(clk_p_i),
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.rclk(clk_p_i),
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.wclk(wb_clk_i),
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.wclk(wb_clk_i),
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.aclr(ctrl_ven),
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.aclr(ctrl_ven),
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.wreq(line_fifo_dpm_wreq),
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.wreq(line_fifo_dpm_wreq),
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.d(line_fifo_dpm_d),
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.d(line_fifo_dpm_d),
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