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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo.v] - Diff between revs 28 and 30
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Rev 30 |
| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_fifo.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
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// $Id: vga_fifo.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
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//
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//
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// $Date: 2002-01-28 03:47:16 $
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// $Date: 2002-02-07 05:42:10 $
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// $Revision: 1.5 $
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// $Revision: 1.6 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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fifo_cnt <= #1 fifo_cnt - 1;
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fifo_cnt <= #1 fifo_cnt - 1;
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end
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end
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// status flags
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// status flags
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assign empty = !(|fifo_cnt);
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assign empty = !(|fifo_cnt);
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assign hfull = fifo_cnt[AWIDTH -1];
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assign hfull = fifo_cnt[AWIDTH -1] | fifo_cnt[AWIDTH];
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assign full = fifo_cnt[AWIDTH];
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assign full = fifo_cnt[AWIDTH];
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endmodule
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endmodule
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