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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_wb_master.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
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// $Id: vga_wb_master.v,v 1.7 2002-02-16 10:40:00 rherveille Exp $
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//
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//
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// $Date: 2002-02-07 05:42:10 $
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// $Date: 2002-02-16 10:40:00 $
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// $Revision: 1.6 $
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// $Revision: 1.7 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/02/07 05:42:10 rherveille
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// Fixed some bugs discovered by modified testbench
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// Removed / Changed some strange logic constructions
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// Started work on hardware cursor support (not finished yet)
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// Changed top-level name to vga_enh_top.v
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "vga_defines.v"
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`include "vga_defines.v"
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module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
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module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
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wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;
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wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;
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wire color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;
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wire color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;
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wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;
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wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;
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wire ImDoneFifoQ;
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wire ImDoneFifoQ;
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reg dImDoneFifoQ, ddImDoneFifoQ;
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reg dImDoneFifoQ, ddImDoneFifoQ;
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reg [2:0] ImDoneCursorQ;
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reg sclr; // synchronous clear
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reg sclr; // synchronous clear
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wire [7:0] clut_offs; // color lookup table offset
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wire [7:0] clut_offs; // color lookup table offset
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.clut_offs(clut_offs),
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.clut_offs(clut_offs),
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.clut_q(clut_q)
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.clut_q(clut_q)
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);
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);
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// hookup data-source-selector && hardware cursor module
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// hookup data-source-selector && hardware cursor module
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`ifdef VGA_HWC1
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`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
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reg scursor1_ld;
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reg scursor1_ld;
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reg scursor1_en;
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reg scursor1_en;
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reg [31:0] scursor1_xy;
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reg [31:0] scursor1_xy;
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reg sddImDoneFifoQ, sdImDoneFifoQ;
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always@(posedge clk_i)
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if (ssel1_wreq)
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begin
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sdImDoneFifoQ <= #1 dImDoneFifoQ;
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sddImDoneFifoQ <= #1 sdImDoneFifoQ;
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end
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (sclr)
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if (sclr)
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scursor1_ld <= #1 1'b0;
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scursor1_ld <= #1 1'b0;
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else
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else
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Line 437... |
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (scursor1_ld)
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if (scursor1_ld)
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scursor1_xy <= #1 cursor1_xy;
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scursor1_xy <= #1 cursor1_xy;
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vga_ssel ssel_and_hw_cursor1 (
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vga_curproc hw_cursor1 (
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.clk(clk_i),
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.clk(clk_i),
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.rst_i(sclr),
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.rst_i(sclr),
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.Thgate(Thgate),
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.Thgate(Thgate),
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.Tvgate(Tvgate),
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.Tvgate(Tvgate),
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.idat(color_proc_q),
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.idat(color_proc_q),
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.cursor_we(cursor1_we),
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.cursor_we(cursor1_we),
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.cursor_dat(dat_i),
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.cursor_dat(dat_i),
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.rgb_fifo_wreq(ssel1_wreq),
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.rgb_fifo_wreq(ssel1_wreq),
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.rgb(ssel1_q)
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.rgb(ssel1_q)
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);
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);
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`else
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wire sddImDoneFifoQ, sdImDoneFifoQ;
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`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
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reg sddImDoneFifoQ, sdImDoneFifoQ;
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always@(posedge clk_i)
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if (ssel1_wreq)
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begin
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sdImDoneFifoQ <= #1 dImDoneFifoQ;
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sddImDoneFifoQ <= #1 sdImDoneFifoQ;
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end
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`endif
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`else // Hardware Cursor1 disabled, generate pass-through signals
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assign ssel1_wreq = color_proc_wreq;
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assign ssel1_wreq = color_proc_wreq;
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assign ssel1_q = color_proc_q;
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assign ssel1_q = color_proc_q;
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`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
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wire sddImDoneFifoQ, sdImDoneFifoQ;
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assign sdImDoneFifoQ = dImDoneFifoQ;
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assign sdImDoneFifoQ = dImDoneFifoQ;
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assign sddImDoneFifoQ = ddImDoneFifoQ;
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assign sddImDoneFifoQ = ddImDoneFifoQ;
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`endif
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`endif
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`ifdef VGA_HWC0
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`endif
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`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
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reg scursor0_ld;
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reg scursor0_ld;
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reg scursor0_en;
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reg scursor0_en;
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reg [31:0] scursor0_xy;
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reg [31:0] scursor0_xy;
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always@(posedge clk_i)
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always@(posedge clk_i)
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Line 500... |
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (scursor0_ld)
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if (scursor0_ld)
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scursor0_xy <= #1 cursor0_xy;
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scursor0_xy <= #1 cursor0_xy;
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vga_ssel ssel_and_hw_cursor0 (
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vga_curproc hw_cursor0 (
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.clk(clk_i),
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.clk(clk_i),
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.rst_i(sclr),
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.rst_i(sclr),
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.Thgate(Thgate),
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.Thgate(Thgate),
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.Tvgate(Tvgate),
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.Tvgate(Tvgate),
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.idat(ssel1_q),
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.idat(ssel1_q),
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.cursor_we(cursor0_we),
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.cursor_we(cursor0_we),
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.cursor_dat(dat_i),
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.cursor_dat(dat_i),
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.rgb_fifo_wreq(rgb_fifo_wreq),
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.rgb_fifo_wreq(rgb_fifo_wreq),
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.rgb(rgb_fifo_d)
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.rgb(rgb_fifo_d)
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);
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);
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`else
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`else // Hardware Cursor0 disabled, generate pass-through signals
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assign rgb_fifo_wreq = ssel1_wreq;
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assign rgb_fifo_wreq = ssel1_wreq;
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assign rgb_fifo_d = ssel1_q;
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assign rgb_fifo_d = ssel1_q;
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`endif
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`endif
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// hookup RGB buffer (temporary station between WISHBONE-clock-domain and pixel-clock-domain)
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// hookup RGB buffer (temporary station between WISHBONE-clock-domain and pixel-clock-domain)
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