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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_wb_master.v,v 1.8 2002-03-04 11:01:59 rherveille Exp $
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// $Id: vga_wb_master.v,v 1.9 2002-03-04 16:05:52 rherveille Exp $
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//
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//
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// $Date: 2002-03-04 11:01:59 $
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// $Date: 2002-03-04 16:05:52 $
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// $Revision: 1.8 $
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// $Revision: 1.9 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/03/04 11:01:59 rherveille
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// Added 64x64pixels 4bpp hardware cursor support.
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//
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// Revision 1.7 2002/02/16 10:40:00 rherveille
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// Revision 1.7 2002/02/16 10:40:00 rherveille
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// Some minor bug-fixes.
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// Some minor bug-fixes.
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// Changed vga_ssel into vga_curproc (cursor processor).
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// Changed vga_ssel into vga_curproc (cursor processor).
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//
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//
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// Revision 1.6 2002/02/07 05:42:10 rherveille
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// Revision 1.6 2002/02/07 05:42:10 rherveille
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| Line 161... |
Line 164... |
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reg sclr; // synchronous clear
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reg sclr; // synchronous clear
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wire [7:0] clut_offs; // color lookup table offset
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wire [7:0] clut_offs; // color lookup table offset
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reg [8:0] cursor_adr;
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//
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reg cursor0_we, cursor1_we;
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// hardware cursors
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reg [31:11] cursor_ba; // cursor pattern base address
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reg [ 8: 0] cursor_adr; // cursor pattern offset
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wire cursor0_we, cursor1_we; // cursor buffers write_request
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reg ld_cursor0, ld_cursor1; // reload cursor0, cursor1
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reg cur_acc; // cursor processors request memory access
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reg cur_acc_sel; // which cursor to reload
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wire cur_ack; // cursor processor memory access acknowledge
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wire cur_done; // done reading cursor pattern
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//
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//
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// module body
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// module body
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//
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//
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| Line 183... |
Line 195... |
reg [31:2] vmemA; // video memory address
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reg [31:2] vmemA; // video memory address
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// wishbone access controller, video memory access request has highest priority (try to keep fifo full)
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// wishbone access controller, video memory access request has highest priority (try to keep fifo full)
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (sclr)
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if (sclr)
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vmem_acc <= #1 1'b0;
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vmem_acc <= #1 1'b0; // video memory access request
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else
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vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc;
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always@(posedge clk_i)
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if (sclr)
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cur_acc <= #1 1'b0; // cursor processor memory access request
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else
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else
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vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone;
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cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done;
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assign vmem_ack = ack_i;
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assign vmem_ack = ack_i & vmem_acc;
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assign cur_ack = ack_i & cur_acc;
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assign sint = err_i; // Non recoverable error, interrupt host system
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assign sint = err_i; // Non recoverable error, interrupt host system
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// select active memory page
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// select active memory page
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assign vmem_switch = ImDoneStrb;
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assign vmem_switch = ImDoneStrb;
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (sclr)
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if (sclr)
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| Line 216... |
Line 237... |
.empty(),
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.empty(),
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.hfull(),
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.hfull(),
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.full()
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.full()
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);
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);
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//
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// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
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// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (sclr)
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if (sclr)
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dImDoneFifoQ <= #1 1'b0;
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dImDoneFifoQ <= #1 1'b0;
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else if (data_fifo_rreq)
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else if (data_fifo_rreq)
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| Line 237... |
Line 259... |
if (sclr)
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if (sclr)
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stat_acmp <= #1 1'b0;
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stat_acmp <= #1 1'b0;
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else if (ctrl_cbsw)
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else if (ctrl_cbsw)
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stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)
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stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)
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//
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// generate clut-address
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// generate clut-address
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assign clut_adr = {stat_acmp, clut_offs};
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assign clut_adr = {stat_acmp, clut_offs};
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//
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// generate burst counter
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// generate burst counter
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wire [3:0] burst_cnt_val;
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wire [3:0] burst_cnt_val;
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assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
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assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
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assign burst_done = burst_cnt_val[3];
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assign burst_done = burst_cnt_val[3];
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| Line 358... |
Line 382... |
else
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else
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vmemA <= #1 VBAb;
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vmemA <= #1 VBAb;
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else if (vmem_ack)
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else if (vmem_ack)
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vmemA <= #1 vmemA +30'h1;
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vmemA <= #1 vmemA +30'h1;
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////////////////////////////////////
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// hardware cursor signals section
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//
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always@(posedge clk_i)
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if (ImDone)
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cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority
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always@(posedge clk_i)
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if (sclr)
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begin
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ld_cursor0 <= #1 1'b0;
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ld_cursor1 <= #1 1'b0;
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end
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else
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begin
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ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done & cur_acc_sel));
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ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel));
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end
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// select cursor base address
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always@(posedge clk_i)
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if (!cur_acc)
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cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba;
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// generate pattern offset
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wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1;
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assign cur_done = next_cursor_adr[9];
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always@(posedge clk_i)
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if (!cur_acc)
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cursor_adr <= #1 9'h0;
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else if (cur_ack)
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cursor_adr <= #1 next_cursor_adr;
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// generate cursor buffers write enable signals
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assign cursor1_we = cur_ack & !cur_acc_sel;
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assign cursor0_we = cur_ack & cur_acc_sel;
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//////////////////////////////
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// generate wishbone signals
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// generate wishbone signals
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assign adr_o = {vmemA, 2'b00};
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//
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wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone;
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assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
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wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone ||
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cur_acc & !cur_done;
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always@(posedge clk_i or negedge nrst_i)
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always@(posedge clk_i or negedge nrst_i)
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if (!nrst_i)
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if (!nrst_i)
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begin
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begin
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cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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| Line 389... |
Line 456... |
sel_o <= #1 4'b1111; // only 32bit accesses are supported
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sel_o <= #1 4'b1111; // only 32bit accesses are supported
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cab_o <= #1 wb_cycle;
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cab_o <= #1 wb_cycle;
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we_o <= #1 1'b0; // read only
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we_o <= #1 1'b0; // read only
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end
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end
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//
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// video-data buffer (temporary store data read from video memory)
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// video-data buffer (temporary store data read from video memory)
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vga_fifo #(4, 32) data_fifo (
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vga_fifo #(4, 32) data_fifo (
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.clk(clk_i),
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.clk(clk_i),
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.aclr(1'b1),
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.aclr(1'b1),
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.sclr(sclr),
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.sclr(sclr),
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| Line 405... |
Line 473... |
.full()
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.full()
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);
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);
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assign nvmem_req = data_fifo_hfull;
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assign nvmem_req = data_fifo_hfull;
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//
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// hookup color processor
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// hookup color processor
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vga_colproc color_proc (
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vga_colproc color_proc (
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.clk(clk_i),
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.clk(clk_i),
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.srst(sclr),
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.srst(sclr),
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.vdat_buffer_di(data_fifo_q),
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.vdat_buffer_di(data_fifo_q),
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| Line 426... |
Line 494... |
.clut_ack(clut_ack),
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.clut_ack(clut_ack),
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.clut_offs(clut_offs),
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.clut_offs(clut_offs),
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.clut_q(clut_q)
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.clut_q(clut_q)
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);
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);
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//
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// hookup data-source-selector && hardware cursor module
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// hookup data-source-selector && hardware cursor module
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`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
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`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
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reg scursor1_ld;
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wire cursor1_ld_strb;
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reg scursor1_en;
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reg scursor1_en;
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reg scursor1_res;
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reg scursor1_res;
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reg [31:0] scursor1_xy;
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reg [31:0] scursor1_xy;
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always@(posedge clk_i)
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assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ;
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if (sclr)
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scursor1_ld <= #1 1'b0;
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else
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scursor1_ld <= #1 cursor1_ld | (scursor1_ld & !(ddImDoneFifoQ & !dImDoneFifoQ));
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (sclr)
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if (sclr)
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scursor1_en <= #1 1'b0;
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scursor1_en <= #1 1'b0;
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else if (scursor1_ld)
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else if (cursor1_ld_strb)
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scursor1_en <= #1 cursor1_en;
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scursor1_en <= #1 cursor1_en;
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (scursor1_ld)
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if (cursor1_ld_strb)
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scursor1_xy <= #1 cursor1_xy;
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scursor1_xy <= #1 cursor1_xy;
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (scursor1_ld)
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if (cursor1_ld_strb)
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scursor1_res <= #1 cursor1_res;
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scursor1_res <= #1 cursor1_res;
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vga_curproc hw_cursor1 (
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vga_curproc hw_cursor1 (
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.clk(clk_i),
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.clk(clk_i),
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.rst_i(sclr),
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.rst_i(sclr),
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| Line 484... |
Line 549... |
sddImDoneFifoQ <= #1 sdImDoneFifoQ;
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sddImDoneFifoQ <= #1 sdImDoneFifoQ;
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end
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end
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`endif
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`endif
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`else // Hardware Cursor1 disabled, generate pass-through signals
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`else // Hardware Cursor1 disabled, generate pass-through signals
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assign ssel1_wreq = color_proc_wreq;
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assign ssel1_wreq = color_proc_wreq;
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assign ssel1_q = color_proc_q;
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assign ssel1_q = color_proc_q;
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assign cc1_adr_0 = 4'h0;
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assign cc1_adr_0 = 4'h0;
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| Line 501... |
Line 565... |
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`endif
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`endif
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`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
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`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
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reg scursor0_ld;
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wire cursor0_ld_strb;
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reg scursor0_en;
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reg scursor0_en;
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reg scursor0_res;
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reg scursor0_res;
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reg [31:0] scursor0_xy;
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reg [31:0] scursor0_xy;
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always@(posedge clk_i)
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assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ;
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if (sclr)
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scursor0_ld <= #1 1'b0;
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else
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scursor0_ld <= #1 cursor0_ld | (scursor0_ld & !(sddImDoneFifoQ & !sdImDoneFifoQ));
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (sclr)
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if (sclr)
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scursor0_en <= #1 1'b0;
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scursor0_en <= #1 1'b0;
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else if (scursor0_ld)
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else if (cursor0_ld_strb)
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scursor0_en <= #1 cursor0_en;
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scursor0_en <= #1 cursor0_en;
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (scursor0_ld)
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if (cursor0_ld_strb)
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scursor0_xy <= #1 cursor0_xy;
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scursor0_xy <= #1 cursor0_xy;
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always@(posedge clk_i)
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always@(posedge clk_i)
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if (scursor0_ld)
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if (cursor0_ld_strb)
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scursor0_res <= #1 cursor0_res;
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scursor0_res <= #1 cursor0_res;
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vga_curproc hw_cursor0 (
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vga_curproc hw_cursor0 (
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.clk(clk_i),
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.clk(clk_i),
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.rst_i(sclr),
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.rst_i(sclr),
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| Line 551... |
Line 611... |
assign rgb_fifo_d = ssel1_q;
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assign rgb_fifo_d = ssel1_q;
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assign cc0_adr_o = 4'h0;
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assign cc0_adr_o = 4'h0;
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`endif
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`endif
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//
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// hookup RGB buffer (temporary station between WISHBONE-clock-domain
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// hookup RGB buffer (temporary station between WISHBONE-clock-domain
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// and pixel-clock-domain)
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// and pixel-clock-domain)
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// The cursor_processor pipelines introduce a delay between the color
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// The cursor_processor pipelines introduce a delay between the color
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// processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate
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// processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate
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// for this we double the rgb_fifo.
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// for this we double the rgb_fifo.
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| Line 575... |
Line 636... |
assign line_fifo_wreq = rgb_fifo_rreq;
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assign line_fifo_wreq = rgb_fifo_rreq;
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endmodule
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endmodule
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No newline at end of file
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