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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_wb_master.v,v 1.12 2003-03-18 21:45:48 rherveille Exp $
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// $Id: vga_wb_master.v,v 1.13 2003-03-19 12:50:45 rherveille Exp $
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//
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//
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// $Date: 2003-03-18 21:45:48 $
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// $Date: 2003-03-19 12:50:45 $
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// $Revision: 1.12 $
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// $Revision: 1.13 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2003/03/18 21:45:48 rherveille
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// Added WISHBONE revB.3 Registered Feedback Cycles support
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//
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// Revision 1.11 2002/04/20 10:02:39 rherveille
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// Revision 1.11 2002/04/20 10:02:39 rherveille
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// Changed video timing generator.
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// Changed video timing generator.
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// Changed wishbone master vertical gate count code.
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// Changed wishbone master vertical gate count code.
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// Fixed a potential bug in the wishbone slave (cursor color register readout).
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// Fixed a potential bug in the wishbone slave (cursor color register readout).
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//
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//
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hgate_div_cnt <= #1 hgate_div_val[1:0];
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hgate_div_cnt <= #1 hgate_div_val[1:0];
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end
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end
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// vgate counter
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// vgate counter
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reg [15:0] vgate_cnt;
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reg [15:0] vgate_cnt;
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wire vdone = ~|vgate_cnt[15:1] & vgate_cnt[0];
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wire [16:0] vgate_cnt_val;
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wire vdone;
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assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
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assign vdone = vgate_cnt_val[16];
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (sclr || ImDoneStrb)
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if (sclr || ImDoneStrb)
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vgate_cnt <= #1 Tvgate;
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vgate_cnt <= #1 Tvgate;
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else if (hdone)
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else if (hdone)
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vgate_cnt <= #1 vgate_cnt -16'h1;
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vgate_cnt <= #1 vgate_cnt_val[15:0];
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assign ImDone = hdone & vdone;
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assign ImDone = hdone & vdone;
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assign ImDoneStrb = ImDone & !dImDone;
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assign ImDoneStrb = ImDone & !dImDone;
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