| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_wb_master.v,v 1.13 2003-03-19 12:50:45 rherveille Exp $
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// $Id: vga_wb_master.v,v 1.14 2003-05-07 09:48:54 rherveille Exp $
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//
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//
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// $Date: 2003-03-19 12:50:45 $
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// $Date: 2003-05-07 09:48:54 $
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// $Revision: 1.13 $
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// $Revision: 1.14 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/03/19 12:50:45 rherveille
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// Changed timing generator; made it smaller and easier.
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//
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// Revision 1.12 2003/03/18 21:45:48 rherveille
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// Revision 1.12 2003/03/18 21:45:48 rherveille
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// Added WISHBONE revB.3 Registered Feedback Cycles support
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// Added WISHBONE revB.3 Registered Feedback Cycles support
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//
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//
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// Revision 1.11 2002/04/20 10:02:39 rherveille
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// Revision 1.11 2002/04/20 10:02:39 rherveille
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// Changed video timing generator.
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// Changed video timing generator.
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| Line 75... |
Line 78... |
// Removed / Changed some strange logic constructions
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// Removed / Changed some strange logic constructions
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// Started work on hardware cursor support (not finished yet)
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// Started work on hardware cursor support (not finished yet)
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// Changed top-level name to vga_enh_top.v
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// Changed top-level name to vga_enh_top.v
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//
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//
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//synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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`include "vga_defines.v"
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//synopsys translate_on
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|
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module vga_wb_master (clk_i, rst_i, nrst_i,
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module vga_wb_master (clk_i, rst_i, nrst_i,
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cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
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cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
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ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw,
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ctrl_ven, ctrl_cd, ctrl_vbl, ctrl_vbsw, busy,
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cursor0_en, cursor0_res, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_o, cc0_dat_i,
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cursor1_en, cursor1_res, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_o, cc1_dat_i,
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VBAa, VBAb, Thgate, Tvgate,
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VBAa, VBAb, Thgate, Tvgate,
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stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,
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stat_avmp, vmem_switch, ImDoneFifoQ,
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clut_req, clut_ack, clut_adr, clut_q);
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cursor_adr, cursor0_ba, cursor1_ba, cursor0_ld, cursor1_ld,
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fb_data_fifo_rreq, fb_data_fifo_q, fb_data_fifo_empty);
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// inputs & outputs
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// inputs & outputs
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|
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// wishbone signals
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// wishbone signals
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input clk_i; // master clock input
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input clk_i; // master clock input
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| Line 97... |
Line 100... |
input nrst_i; // asynchronous low reset
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input nrst_i; // asynchronous low reset
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output cyc_o; // cycle output
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output cyc_o; // cycle output
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reg cyc_o;
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reg cyc_o;
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output stb_o; // strobe ouput
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output stb_o; // strobe ouput
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reg stb_o;
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reg stb_o;
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output [ 3:0] cti_o; // cycle type id
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output [ 2:0] cti_o; // cycle type id
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reg [3:0] cti_o;
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reg [2:0] cti_o;
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output [ 1:0] bte_o; // burst type extension
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output [ 1:0] bte_o; // burst type extension
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reg [1:0] bte_o;
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reg [1:0] bte_o;
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output we_o; // write enable output
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output we_o; // write enable output
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reg we_o;
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reg we_o;
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output [31:0] adr_o; // address output
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output [31:0] adr_o; // address output
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| Line 115... |
Line 118... |
output sint; // non recoverable error, interrupt host
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output sint; // non recoverable error, interrupt host
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|
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// control register settings
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// control register settings
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input ctrl_ven; // video enable bit
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input ctrl_ven; // video enable bit
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input [1:0] ctrl_cd; // color depth
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input [1:0] ctrl_cd; // color depth
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input ctrl_pc; // 8bpp pseudo color/bw
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input [1:0] ctrl_vbl; // burst length
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input [1:0] ctrl_vbl; // burst length
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input ctrl_vbsw; // enable video bank switching
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input ctrl_vbsw; // enable video bank switching
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input ctrl_cbsw; // enable clut bank switching
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output busy; // data transfer in progress
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input cursor0_en; // enable hardware cursor0
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input cursor0_res; // cursor0 resolution
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input [31: 0] cursor0_xy; // (x,y) address hardware cursor0
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input [31:11] cursor0_ba; // cursor0 video memory base address
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input cursor0_ld; // reload cursor0 from video memory
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output [ 3: 0] cc0_adr_o; // cursor0 color registers address output
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input [15: 0] cc0_dat_i; // cursor0 color registers data input
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input cursor1_en; // enable hardware cursor1
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input cursor1_res; // cursor1 resolution
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input [31: 0] cursor1_xy; // (x,y) address hardware cursor1
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input [31:11] cursor1_ba; // cursor1 video memory base address
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input cursor1_ld; // reload cursor1 from video memory
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output [ 3: 0] cc1_adr_o; // cursor1 color registers address output
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input [15: 0] cc1_dat_i; // cursor1 color registers data input
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// video memory addresses
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// video memory addresses
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input [31: 2] VBAa; // video memory base address A
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input [31: 2] VBAa; // video memory base address A
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input [31: 2] VBAb; // video memory base address B
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input [31: 2] VBAb; // video memory base address B
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input [15:0] Thgate; // horizontal visible area (in pixels)
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input [15:0] Thgate; // horizontal visible area (in pixels)
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input [15:0] Tvgate; // vertical visible area (in horizontal lines)
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input [15:0] Tvgate; // vertical visible area (in horizontal lines)
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|
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output stat_avmp; // active video memory page
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output stat_avmp; // active video memory page
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output stat_acmp; // active CLUT memory page
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reg stat_acmp;
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output vmem_switch; // video memory bank-switch request: memory page switched (when enabled)
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output vmem_switch; // video memory bank-switch request: memory page switched (when enabled)
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output clut_switch; // clut memory bank-switch request: clut page switched (when enabled)
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output ImDoneFifoQ;
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output [ 8: 0] cursor_adr; // cursor address
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input [31:11] cursor0_ba;
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input [31:11] cursor1_ba;
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input cursor0_ld; // load cursor0 (from wbs)
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input cursor1_ld; // load cursor1 (from wbs)
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input fb_data_fifo_rreq;
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output [31: 0] fb_data_fifo_q;
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output fb_data_fifo_empty;
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// to/from line-fifo
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output line_fifo_wreq;
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output [23:0] line_fifo_d;
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input line_fifo_full;
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// to/from color lookup-table
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output clut_req; // clut access request
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input clut_ack; // clut access acknowledge
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output [ 8:0] clut_adr; // clut access address
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input [23:0] clut_q; // clut access data in
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//
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//
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// variable declarations
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// variable declarations
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//
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//
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reg vmem_acc; // video memory access
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reg vmem_acc; // video memory access
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wire vmem_req_n, vmem_ack; // NOT video memory access request // video memory access acknowledge
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wire vmem_req, vmem_ack; // video memory access request // video memory access acknowledge
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wire ImDone; // Done reading image from video mem
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wire ImDone; // Done reading image from video mem
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reg dImDone; // delayed ImDone
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reg dImDone; // delayed ImDone
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wire ImDoneStrb; // image done (strobe signal)
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wire ImDoneStrb; // image done (strobe signal)
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reg dImDoneStrb; // delayed ImDoneStrb
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reg dImDoneStrb; // delayed ImDoneStrb
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wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull;
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reg sclr; // (video/cursor) synchronous clear
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wire [31:0] data_fifo_q;
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wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;
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wire color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;
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wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;
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wire ImDoneFifoQ;
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reg dImDoneFifoQ, ddImDoneFifoQ;
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reg sclr; // synchronous clear
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wire [7:0] clut_offs; // color lookup table offset
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//
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// hardware cursors
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// hardware cursors
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reg [31:11] cursor_ba; // cursor pattern base address
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reg [31:11] cursor_ba; // cursor pattern base address
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reg [ 8: 0] cursor_adr; // cursor pattern offset
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reg [ 8: 0] cursor_adr; // cursor pattern offset
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wire cursor0_we, cursor1_we; // cursor buffers write_request
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wire cursor0_we, cursor1_we; // cursor buffers write_request
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reg ld_cursor0, ld_cursor1; // reload cursor0, cursor1
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reg ld_cursor0, ld_cursor1; // reload cursor0, cursor1
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reg cur_acc; // cursor processors request memory access
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reg cur_acc; // cursor processors request memory access
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reg cur_acc_sel; // which cursor to reload
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reg cur_acc_sel; // which cursor to reload
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wire cur_ack; // cursor processor memory access acknowledge
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wire cur_ack; // cursor processor memory access acknowledge
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wire cur_done; // done reading cursor pattern
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wire cur_done; // done reading cursor pattern
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//
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//
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// module body
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// module body
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//
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//
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// generate synchronous clear
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// generate synchronous clear
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| Line 216... |
Line 189... |
// wishbone access controller, video memory access request has highest priority (try to keep fifo full)
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// wishbone access controller, video memory access request has highest priority (try to keep fifo full)
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (sclr)
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if (sclr)
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vmem_acc <= #1 1'b0; // video memory access request
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vmem_acc <= #1 1'b0; // video memory access request
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else
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else
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vmem_acc <= #1 (!vmem_req_n | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc;
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vmem_acc <= #1 (vmem_req | (vmem_acc & !(burst_done & vmem_ack)) ) & !ImDone & !cur_acc;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (sclr)
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if (sclr)
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cur_acc <= #1 1'b0; // cursor processor memory access request
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cur_acc <= #1 1'b0; // cursor processor memory access request
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else
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else
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cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done;
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cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done;
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assign busy = vmem_acc | cur_acc;
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assign vmem_ack = ack_i & stb_o & vmem_acc;
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assign vmem_ack = ack_i & stb_o & vmem_acc;
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assign cur_ack = ack_i & stb_o & cur_acc;
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assign cur_ack = ack_i & stb_o & cur_acc;
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assign sint = err_i; // Non recoverable error, interrupt host system
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assign sint = err_i; // Non recoverable error, interrupt host system
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| Line 250... |
Line 224... |
.aclr(1'b1),
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.aclr(1'b1),
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.sclr(sclr),
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.sclr(sclr),
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.d(ImDone),
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.d(ImDone),
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.wreq(vmem_ack),
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.wreq(vmem_ack),
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.q(ImDoneFifoQ),
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.q(ImDoneFifoQ),
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.rreq(data_fifo_rreq),
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.rreq ( fb_data_fifo_rreq ),
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.nword ( ),
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.empty(),
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.empty(),
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.hfull(),
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.full ( ),
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.full()
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.aempty ( ),
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.afull ( )
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);
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);
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//
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// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
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always @(posedge clk_i)
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if (sclr)
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dImDoneFifoQ <= #1 1'b0;
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else if (data_fifo_rreq)
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dImDoneFifoQ <= #1 ImDoneFifoQ;
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always @(posedge clk_i)
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if (sclr)
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ddImDoneFifoQ <= #1 1'b0;
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else
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ddImDoneFifoQ <= #1 dImDoneFifoQ;
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assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;
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always @(posedge clk_i)
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if (sclr)
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stat_acmp <= #1 1'b0;
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else if (ctrl_cbsw)
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stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)
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//
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// generate clut-address
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assign clut_adr = {stat_acmp, clut_offs};
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//
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//
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// generate burst counter
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// generate burst counter
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wire [3:0] burst_cnt_val;
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wire [3:0] burst_cnt_val;
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assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
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assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
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| Line 366... |
Line 317... |
|
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assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
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assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
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assign vdone = vgate_cnt_val[16];
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assign vdone = vgate_cnt_val[16];
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|
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (sclr || ImDoneStrb)
|
if (sclr | ImDoneStrb)
|
vgate_cnt <= #1 Tvgate;
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vgate_cnt <= #1 Tvgate;
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else if (hdone)
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else if (hdone)
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vgate_cnt <= #1 vgate_cnt_val[15:0];
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vgate_cnt <= #1 vgate_cnt_val[15:0];
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|
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assign ImDone = hdone & vdone;
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assign ImDone = hdone & vdone;
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| Line 387... |
Line 338... |
// generate addresses
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// generate addresses
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//
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//
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|
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// select video memory base address
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// select video memory base address
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (dImDoneStrb | sclr)
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if (sclr | dImDoneStrb)
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if (!sel_VBA)
|
if (!sel_VBA)
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vmemA <= #1 VBAa;
|
vmemA <= #1 VBAa;
|
else
|
else
|
vmemA <= #1 VBAb;
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vmemA <= #1 VBAb;
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else if (vmem_ack)
|
else if (vmem_ack)
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| Line 439... |
Line 390... |
|
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//////////////////////////////
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//////////////////////////////
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// generate wishbone signals
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// generate wishbone signals
|
//
|
//
|
assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
|
assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
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wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & vmem_req_n) & !ImDone ||
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wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & !vmem_req) & !ImDone ||
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cur_acc & !cur_done;
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cur_acc & !cur_done;
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|
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wire [2:0] cti_vid = (burst_cnt == 3'h1) ? 3'b111 : 3'b010;
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wire [2:0] cti_cur = &next_cursor_adr[8:0] ? 3'b111 : 3'b010;
|
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reg [2:0] cti;
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always @(ctrl_vbl or cur_acc or cti_cur or cti_vid)
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case (ctrl_vbl)
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3'b000: cti <= #1 3'b000; // wishbone classic cycle
|
|
|
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default: cti <= #1 cur_acc ? cti_cur : cti_vid;
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endcase
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|
|
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always @(posedge clk_i or negedge nrst_i)
|
always @(posedge clk_i or negedge nrst_i)
|
if (!nrst_i)
|
if (!nrst_i)
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
| Line 477... |
Line 418... |
else
|
else
|
begin
|
begin
|
cyc_o <= #1 wb_cycle;
|
cyc_o <= #1 wb_cycle;
|
stb_o <= #1 wb_cycle;
|
stb_o <= #1 wb_cycle;
|
sel_o <= #1 4'b1111; // only 32bit accesses are supported
|
sel_o <= #1 4'b1111; // only 32bit accesses are supported
|
we_o <= #1 1'b0; // read only
|
|
|
|
if (vmem_ack | cur_ack)
|
if (wb_cycle) begin
|
cti_o <= #1 cti; // cycle type
|
if (cur_acc)
|
|
cti_o <= #1 &next_cursor_adr[8:0] ? 3'b111 : 3'b010;
|
|
else if (ctrl_vbl == 2'b00)
|
|
cti_o <= #1 3'b000;
|
|
else if (vmem_ack)
|
|
cti_o <= #1 (burst_cnt == 3'h1) ? 3'b111 : 3'b010;
|
|
end else
|
|
cti_o <= #1 (ctrl_vbl == 2'b00) ? 3'b000 : 3'b010;
|
|
|
bte_o <= #1 2'b00; // linear burst
|
bte_o <= #1 2'b00; // linear burst
|
|
we_o <= #1 1'b0; // read only
|
end
|
end
|
|
|
//
|
//
|
// video-data buffer (temporary store data read from video memory)
|
// video-data buffer (temporary store data read from video memory)
|
|
wire [3:0] fb_data_fifo_nword;
|
|
wire fb_data_fifo_full;
|
|
|
vga_fifo #(4, 32) data_fifo (
|
vga_fifo #(4, 32) data_fifo (
|
.clk(clk_i),
|
.clk(clk_i),
|
.aclr(1'b1),
|
.aclr(1'b1),
|
.sclr(sclr),
|
.sclr(sclr),
|
.d(dat_i),
|
.d(dat_i),
|
.wreq(vmem_ack),
|
.wreq(vmem_ack),
|
.q(data_fifo_q),
|
.q ( fb_data_fifo_q ),
|
.rreq(data_fifo_rreq),
|
.rreq ( fb_data_fifo_rreq ),
|
.empty(data_fifo_empty),
|
.nword ( fb_data_fifo_nword ),
|
.hfull(data_fifo_hfull),
|
.empty ( fb_data_fifo_empty ),
|
.full()
|
.full ( fb_data_fifo_full ),
|
);
|
.aempty ( ),
|
|
.afull ( )
|
assign vmem_req_n = data_fifo_hfull;
|
|
|
|
//
|
|
// hookup color processor
|
|
vga_colproc color_proc (
|
|
.clk(clk_i),
|
|
.srst(sclr),
|
|
.vdat_buffer_di(data_fifo_q),
|
|
.ColorDepth(ctrl_cd),
|
|
.PseudoColor(ctrl_pc),
|
|
.vdat_buffer_empty(data_fifo_empty),
|
|
.vdat_buffer_rreq(data_fifo_rreq),
|
|
.rgb_fifo_full(rgb_fifo_full),
|
|
.rgb_fifo_wreq(color_proc_wreq),
|
|
.r(color_proc_q[23:16]),
|
|
.g(color_proc_q[15:8]),
|
|
.b(color_proc_q[7:0]),
|
|
.clut_req(clut_req),
|
|
.clut_ack(clut_ack),
|
|
.clut_offs(clut_offs),
|
|
.clut_q(clut_q)
|
|
);
|
|
|
|
//
|
|
// hookup data-source-selector && hardware cursor module
|
|
`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
|
|
wire cursor1_ld_strb;
|
|
reg scursor1_en;
|
|
reg scursor1_res;
|
|
reg [31:0] scursor1_xy;
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|
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assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ;
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|
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always @(posedge clk_i)
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if (sclr)
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scursor1_en <= #1 1'b0;
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else if (cursor1_ld_strb)
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scursor1_en <= #1 cursor1_en;
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|
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always @(posedge clk_i)
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if (cursor1_ld_strb)
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scursor1_xy <= #1 cursor1_xy;
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|
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always @(posedge clk_i)
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if (cursor1_ld_strb)
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scursor1_res <= #1 cursor1_res;
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|
|
|
vga_curproc hw_cursor1 (
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|
.clk(clk_i),
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|
.rst_i(sclr),
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|
.Thgate(Thgate),
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|
.Tvgate(Tvgate),
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|
.idat(color_proc_q),
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|
.idat_wreq(color_proc_wreq),
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|
.cursor_xy(scursor1_xy),
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|
.cursor_res(scursor1_res),
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|
.cursor_en(scursor1_en),
|
|
.cursor_wadr(cursor_adr),
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|
.cursor_we(cursor1_we),
|
|
.cursor_wdat(dat_i),
|
|
.cc_adr_o(cc1_adr_o),
|
|
.cc_dat_i(cc1_dat_i),
|
|
.rgb_fifo_wreq(ssel1_wreq),
|
|
.rgb(ssel1_q)
|
|
);
|
|
|
|
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
|
|
reg sddImDoneFifoQ, sdImDoneFifoQ;
|
|
|
|
always @(posedge clk_i)
|
|
if (ssel1_wreq)
|
|
begin
|
|
sdImDoneFifoQ <= #1 dImDoneFifoQ;
|
|
sddImDoneFifoQ <= #1 sdImDoneFifoQ;
|
|
end
|
|
`endif
|
|
|
|
`else // Hardware Cursor1 disabled, generate pass-through signals
|
|
assign ssel1_wreq = color_proc_wreq;
|
|
assign ssel1_q = color_proc_q;
|
|
|
|
assign cc1_adr_o = 4'h0;
|
|
|
|
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
|
|
wire sddImDoneFifoQ, sdImDoneFifoQ;
|
|
|
|
assign sdImDoneFifoQ = dImDoneFifoQ;
|
|
assign sddImDoneFifoQ = ddImDoneFifoQ;
|
|
`endif
|
|
|
|
`endif
|
|
|
|
|
|
`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
|
|
wire cursor0_ld_strb;
|
|
reg scursor0_en;
|
|
reg scursor0_res;
|
|
reg [31:0] scursor0_xy;
|
|
|
|
assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ;
|
|
|
|
always @(posedge clk_i)
|
|
if (sclr)
|
|
scursor0_en <= #1 1'b0;
|
|
else if (cursor0_ld_strb)
|
|
scursor0_en <= #1 cursor0_en;
|
|
|
|
always @(posedge clk_i)
|
|
if (cursor0_ld_strb)
|
|
scursor0_xy <= #1 cursor0_xy;
|
|
|
|
always @(posedge clk_i)
|
|
if (cursor0_ld_strb)
|
|
scursor0_res <= #1 cursor0_res;
|
|
|
|
vga_curproc hw_cursor0 (
|
|
.clk(clk_i),
|
|
.rst_i(sclr),
|
|
.Thgate(Thgate),
|
|
.Tvgate(Tvgate),
|
|
.idat(ssel1_q),
|
|
.idat_wreq(ssel1_wreq),
|
|
.cursor_xy(scursor0_xy),
|
|
.cursor_en(scursor0_en),
|
|
.cursor_res(scursor0_res),
|
|
.cursor_wadr(cursor_adr),
|
|
.cursor_we(cursor0_we),
|
|
.cursor_wdat(dat_i),
|
|
.cc_adr_o(cc0_adr_o),
|
|
.cc_dat_i(cc0_dat_i),
|
|
.rgb_fifo_wreq(rgb_fifo_wreq),
|
|
.rgb(rgb_fifo_d)
|
|
);
|
|
`else // Hardware Cursor0 disabled, generate pass-through signals
|
|
assign rgb_fifo_wreq = ssel1_wreq;
|
|
assign rgb_fifo_d = ssel1_q;
|
|
|
|
assign cc0_adr_o = 4'h0;
|
|
`endif
|
|
|
|
//
|
|
// hookup RGB buffer (temporary station between WISHBONE-clock-domain
|
|
// and pixel-clock-domain)
|
|
// The cursor_processor pipelines introduce a delay between the color
|
|
// processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate
|
|
// for this we double the rgb_fifo.
|
|
vga_fifo #(4, 24) rgb_fifo (
|
|
.clk(clk_i),
|
|
.aclr(1'b1),
|
|
.sclr(sclr),
|
|
.d(rgb_fifo_d),
|
|
.wreq(rgb_fifo_wreq),
|
|
.q(line_fifo_d),
|
|
.rreq(rgb_fifo_rreq),
|
|
.empty(rgb_fifo_empty),
|
|
.hfull(rgb_fifo_full),
|
|
.full()
|
|
);
|
);
|
|
|
assign rgb_fifo_rreq = !line_fifo_full && !rgb_fifo_empty;
|
// assign vmem_req = ~(fb_data_fifo_nword[3] | fb_data_fifo_full);
|
assign line_fifo_wreq = rgb_fifo_rreq;
|
assign vmem_req = ~fb_data_fifo_nword[3];
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
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No newline at end of file
|
