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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE rev.B2 compliant VGA/LCD Core; Wishbone Slave ////
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//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////
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//// Wishbone slave interface ////
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//// Wishbone slave interface ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_wb_slave.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
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// $Id: vga_wb_slave.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
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//
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//
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// $Date: 2002-01-28 03:47:16 $
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// $Date: 2002-02-07 05:42:10 $
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// $Revision: 1.5 $
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// $Revision: 1.6 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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`include "timescale.v"
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`include "timescale.v"
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`include "vga_defines.v"
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module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
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module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
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bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp, vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
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bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
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cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
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vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
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Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
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Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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output pc; // pseudo color
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output pc; // pseudo color
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output [1:0] cd; // color depth
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output [1:0] cd; // color depth
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output [1:0] vbl; // video memory burst length
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output [1:0] vbl; // video memory burst length
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output cbsw; // clut bank switch enable
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output cbsw; // clut bank switch enable
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output vbsw; // video memory bank switch enable
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output vbsw; // video memory bank switch enable
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output ven; // vdeio system enable
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output ven; // video system enable
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// hardware cursor settings
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output cursor0_en;
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output [31: 0] cursor0_xy;
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output [31:11] cursor0_ba; // cursor0 base address
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output cursor0_ld; // reload cursor0 from video memory
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output cursor1_en;
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output [31: 0] cursor1_xy;
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output [31:11] cursor1_ba; // cursor1 base address
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output cursor1_ld; // reload cursor1 from video memory
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reg [31: 0] cursor0_xy;
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reg [31:11] cursor0_ba;
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reg cursor0_ld;
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reg [31: 0] cursor1_xy;
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reg [31:11] cursor1_ba;
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reg cursor1_ld;
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// status register inputs
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// status register inputs
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input avmp; // active video memory page
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input avmp; // active video memory page
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input acmp; // active clut memory page
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input acmp; // active clut memory page
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input vbsint_in; // bank switch interrupt request
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input vbsint_in; // bank switch interrupt request
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//
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//
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// variable declarations
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// variable declarations
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//
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//
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wire [2:0] REG_ADR = ADR_I[4:2];
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parameter REG_ADR_HIBIT = 3;
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wire [REG_ADR_HIBIT:0] REG_ADR = ADR_I[REG_ADR_HIBIT +2 : 2];
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wire CLUT_ADR = ADR_I[11];
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wire CLUT_ADR = ADR_I[11];
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parameter [2:0] CTRL_ADR = 3'b000;
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parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 4'b0000;
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parameter [2:0] STAT_ADR = 3'b001;
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parameter [REG_ADR_HIBIT : 0] STAT_ADR = 4'b0001;
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parameter [2:0] HTIM_ADR = 3'b010;
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parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 4'b0010;
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parameter [2:0] VTIM_ADR = 3'b011;
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parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 4'b0011;
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parameter [2:0] HVLEN_ADR = 3'b100;
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parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;
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parameter [2:0] VBARA_ADR = 3'b101;
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parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;
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parameter [2:0] VBARB_ADR = 3'b110;
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parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;
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parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 4'b1000;
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parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;
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parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 4'b1010;
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parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;
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reg [31:0] ctrl, stat, htim, vtim, hvlen;
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reg [31:0] ctrl, stat, htim, vtim, hvlen;
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wire hint, vint, vbsint, cbsint, luint, sint;
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wire hint, vint, vbsint, cbsint, luint, sint;
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wire hie, vie, vbsie, cbsie;
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wire hie, vie, vbsie, cbsie;
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HTIM_ADR : htim <= #1 DAT_I;
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HTIM_ADR : htim <= #1 DAT_I;
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VTIM_ADR : vtim <= #1 DAT_I;
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VTIM_ADR : vtim <= #1 DAT_I;
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HVLEN_ADR : hvlen <= #1 DAT_I;
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HVLEN_ADR : hvlen <= #1 DAT_I;
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VBARA_ADR : VBARa <= #1 DAT_I[31: 2];
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VBARA_ADR : VBARa <= #1 DAT_I[31: 2];
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VBARB_ADR : VBARb <= #1 DAT_I[31: 2];
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VBARB_ADR : VBARb <= #1 DAT_I[31: 2];
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C0XY_ADR : cursor0_xy <= #1 DAT_I[31: 0];
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C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];
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C1XY_ADR : cursor1_xy <= #1 DAT_I[31: 0];
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C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];
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endcase
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endcase
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end
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end
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always@(posedge CLK_I)
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begin
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cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);
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cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);
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end
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// generate control register
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// generate control register
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always@(posedge CLK_I or negedge nRESET)
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always@(posedge CLK_I or negedge nRESET)
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if (!nRESET)
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if (!nRESET)
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ctrl <= #1 0;
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ctrl <= #1 0;
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stat <= #1 0;
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stat <= #1 0;
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else if (RST_I)
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else if (RST_I)
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stat <= #1 0;
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stat <= #1 0;
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else
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else
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begin
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begin
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`ifdef VGA_HWC1
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stat[21] <= #1 1'b1;
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`else
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stat[21] <= #1 1'b0;
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`endif
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`ifdef VGA_HWC0
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stat[20] <= #1 1'b1;
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`else
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stat[20] <= #1 1'b0;
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`endif
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stat[17] <= #1 acmp;
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stat[17] <= #1 acmp;
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stat[16] <= #1 avmp;
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stat[16] <= #1 avmp;
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if (reg_wacc & (REG_ADR == STAT_ADR) )
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if (reg_wacc & (REG_ADR == STAT_ADR) )
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begin
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begin
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stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
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stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
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stat[6] <= #1 vbsint_in | (stat[6] & !DAT_I[6]);
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stat[6] <= #1 vbsint_in | (stat[6] & !DAT_I[6]);
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stat[5] <= #1 hint_in | (stat[5] & !DAT_I[5]);
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stat[5] <= #1 hint_in | (stat[5] & !DAT_I[5]);
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end
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end
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end
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end
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// decode control register
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// decode control register
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assign cursor1_en = ctrl[21];
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assign cursor0_en = ctrl[20];
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assign bl = ctrl[15];
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assign bl = ctrl[15];
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assign csl = ctrl[14];
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assign csl = ctrl[14];
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assign vsl = ctrl[13];
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assign vsl = ctrl[13];
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assign hsl = ctrl[12];
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assign hsl = ctrl[12];
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assign pc = ctrl[11];
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assign pc = ctrl[11];
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HTIM_ADR : reg_dato = htim;
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HTIM_ADR : reg_dato = htim;
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VTIM_ADR : reg_dato = vtim;
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VTIM_ADR : reg_dato = vtim;
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HVLEN_ADR : reg_dato = hvlen;
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HVLEN_ADR : reg_dato = hvlen;
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VBARA_ADR : reg_dato = {VBARa, 2'b0};
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VBARA_ADR : reg_dato = {VBARa, 2'b0};
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VBARB_ADR : reg_dato = {VBARb, 2'b0};
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VBARB_ADR : reg_dato = {VBARb, 2'b0};
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C0XY_ADR : reg_dato = cursor0_xy;
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C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
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C1XY_ADR : reg_dato = cursor1_xy;
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C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
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default : reg_dato = 32'h0000_0000;
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default : reg_dato = 32'h0000_0000;
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endcase
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endcase
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always@(posedge CLK_I)
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always@(posedge CLK_I)
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DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
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DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
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always@(posedge CLK_I)
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always@(posedge CLK_I)
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INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
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INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
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endmodule
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endmodule
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