| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_wb_slave.v,v 1.7 2002-02-25 06:13:44 rherveille Exp $
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// $Id: vga_wb_slave.v,v 1.8 2002-03-04 11:01:59 rherveille Exp $
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//
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//
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// $Date: 2002-02-25 06:13:44 $
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// $Date: 2002-03-04 11:01:59 $
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// $Revision: 1.7 $
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// $Revision: 1.8 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/02/25 06:13:44 rherveille
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// Fixed dat_o incomplete sensitivity list.
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//
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// Revision 1.6 2002/02/07 05:42:10 rherveille
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// Revision 1.6 2002/02/07 05:42:10 rherveille
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// Fixed some bugs discovered by modified testbench
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// Fixed some bugs discovered by modified testbench
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// Removed / Changed some strange logic constructions
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// Removed / Changed some strange logic constructions
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// Started work on hardware cursor support (not finished yet)
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// Started work on hardware cursor support (not finished yet)
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// Changed top-level name to vga_enh_top.v
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// Changed top-level name to vga_enh_top.v
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| Line 56... |
Line 59... |
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`include "timescale.v"
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`include "timescale.v"
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`include "vga_defines.v"
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`include "vga_defines.v"
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module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
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module vga_wb_slave(clk_i, rst_i, arst_i, adr_i, dat_i, dat_o, sel_i, we_i, stb_i, cyc_i, ack_o, err_o, inta_o,
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bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
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bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
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cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
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cursor0_res, cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_i, cc0_dat_o,
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cursor1_res, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_i, cc1_dat_o,
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vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
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vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
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Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
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Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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// wishbone slave interface
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// wishbone slave interface
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input CLK_I;
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input clk_i;
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input RST_I;
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input rst_i;
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input nRESET;
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input arst_i;
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input [11:2] ADR_I;
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input [11:2] adr_i;
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input [31:0] DAT_I;
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input [31:0] dat_i;
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output [31:0] DAT_O;
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output [31:0] dat_o;
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reg [31:0] DAT_O;
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reg [31:0] dat_o;
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input [ 3:0] SEL_I;
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input [ 3:0] sel_i;
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input WE_I;
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input we_i;
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input STB_I;
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input stb_i;
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input CYC_I;
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input cyc_i;
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output ACK_O;
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output ack_o;
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reg ACK_O;
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reg ack_o;
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output ERR_O;
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output err_o;
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reg ERR_O;
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reg err_o;
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output INTA_O;
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output inta_o;
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reg INTA_O;
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reg inta_o;
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// control register settings
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// control register settings
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output bl; // blanking level
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output bl; // blanking level
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output csl; // composite sync level
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output csl; // composite sync level
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output vsl; // vsync level
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output vsl; // vsync level
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| Line 98... |
Line 102... |
output cbsw; // clut bank switch enable
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output cbsw; // clut bank switch enable
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output vbsw; // video memory bank switch enable
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output vbsw; // video memory bank switch enable
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output ven; // video system enable
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output ven; // video system enable
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// hardware cursor settings
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// hardware cursor settings
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output cursor0_en;
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output cursor0_res; // cursor0 resolution
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output [31: 0] cursor0_xy;
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output cursor0_en; // cursor0 enable
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output [31: 0] cursor0_xy; // cursor0 location
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output [31:11] cursor0_ba; // cursor0 base address
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output [31:11] cursor0_ba; // cursor0 base address
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output cursor0_ld; // reload cursor0 from video memory
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output cursor0_ld; // reload cursor0 from video memory
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output cursor1_en;
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input [ 3: 0] cc0_adr_i; // cursor0 color register address
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output [31: 0] cursor1_xy;
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output [15: 0] cc0_dat_o; // cursor0 color register data
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output cursor1_res; // cursor1 resolution
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output cursor1_en; // cursor1 enable
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output [31: 0] cursor1_xy; // cursor1 location
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output [31:11] cursor1_ba; // cursor1 base address
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output [31:11] cursor1_ba; // cursor1 base address
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output cursor1_ld; // reload cursor1 from video memory
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output cursor1_ld; // reload cursor1 from video memory
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input [ 3: 0] cc1_adr_i; // cursor1 color register address
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output [15: 0] cc1_dat_o; // cursor1 color register data
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reg [31: 0] cursor0_xy;
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reg [31: 0] cursor0_xy;
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reg [31:11] cursor0_ba;
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reg [31:11] cursor0_ba;
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reg cursor0_ld;
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reg cursor0_ld;
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reg [31: 0] cursor1_xy;
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reg [31: 0] cursor1_xy;
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| Line 151... |
Line 161... |
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//
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//
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// variable declarations
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// variable declarations
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//
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//
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parameter REG_ADR_HIBIT = 3;
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parameter REG_ADR_HIBIT = 7;
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wire [REG_ADR_HIBIT:0] REG_ADR = ADR_I[REG_ADR_HIBIT +2 : 2];
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wire [REG_ADR_HIBIT:0] REG_ADR = adr_i[REG_ADR_HIBIT : 2];
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wire CLUT_ADR = ADR_I[11];
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wire CLUT_ADR = adr_i[11];
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parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 4'b0000;
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parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 6'b00_0000;
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parameter [REG_ADR_HIBIT : 0] STAT_ADR = 4'b0001;
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parameter [REG_ADR_HIBIT : 0] STAT_ADR = 6'b00_0001;
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parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 4'b0010;
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parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 6'b00_0010;
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parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 4'b0011;
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parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 6'b00_0011;
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parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;
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parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 6'b00_0100;
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parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;
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parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 6'b00_0101;
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parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;
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parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 6'b00_0110;
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parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 4'b1000;
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parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 6'b00_1100;
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parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;
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parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 6'b00_1101;
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parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 4'b1010;
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parameter [REG_ADR_HIBIT : 0] CCR0_ADR = 6'b01_0???;
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parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;
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parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 6'b01_1100;
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parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 6'b01_1101;
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parameter [REG_ADR_HIBIT : 0] CCR1_ADR = 6'b10_0???;
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reg [31:0] ctrl, stat, htim, vtim, hvlen;
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reg [31:0] ctrl, stat, htim, vtim, hvlen;
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wire hint, vint, vbsint, cbsint, luint, sint;
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wire hint, vint, vbsint, cbsint, luint, sint;
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wire hie, vie, vbsie, cbsie;
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wire hie, vie, vbsie, cbsie;
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wire acc, acc32, reg_acc, reg_wacc;
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wire acc, acc32, reg_acc, reg_wacc;
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wire cc0_acc, cc1_acc;
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wire [31:0] ccr0_dat_o, ccr1_dat_o;
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reg [31:0] reg_dato; // data output from registers
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reg [31:0] reg_dato; // data output from registers
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//
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//
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// Module body
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// Module body
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//
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//
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assign acc = CYC_I & STB_I;
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assign acc = cyc_i & stb_i;
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assign acc32 = (SEL_I == 4'b1111);
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assign acc32 = (sel_i == 4'b1111);
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assign clut_acc = CLUT_ADR & acc & acc32;
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assign clut_acc = CLUT_ADR & acc & acc32;
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assign reg_acc = !CLUT_ADR & acc & acc32;
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assign reg_acc = !CLUT_ADR & acc & acc32;
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assign reg_wacc = reg_acc & WE_I;
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assign reg_wacc = reg_acc & we_i;
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assign cc0_acc = CCR0_ADR & acc & acc32;
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assign cc1_acc = CCR1_ADR & acc & acc32;
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always@(posedge CLK_I)
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always@(posedge clk_i)
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ACK_O <= #1 ((reg_acc & acc32) | clut_ack) & !ACK_O;
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ack_o <= #1 ((reg_acc & acc32) | clut_ack) & !ack_o;
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always@(posedge CLK_I)
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always@(posedge clk_i)
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ERR_O <= #1 acc & !acc32;
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err_o <= #1 acc & !acc32 & !err_o;
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// generate registers
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// generate registers
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always@(posedge CLK_I or negedge nRESET)
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always@(posedge clk_i or negedge arst_i)
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begin : gen_regs
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begin : gen_regs
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if(!nRESET)
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if(!arst_i)
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begin
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begin
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htim <= #1 0;
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htim <= #1 0;
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vtim <= #1 0;
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vtim <= #1 0;
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hvlen <= #1 0;
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hvlen <= #1 0;
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VBARa <= #1 0;
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VBARa <= #1 0;
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| Line 209... |
Line 226... |
cursor0_xy <= #1 0;
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cursor0_xy <= #1 0;
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cursor0_ba <= #1 0;
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cursor0_ba <= #1 0;
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cursor1_xy <= #1 0;
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cursor1_xy <= #1 0;
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cursor1_ba <= #1 0;
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cursor1_ba <= #1 0;
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end
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end
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else if (RST_I)
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else if (rst_i)
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begin
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begin
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htim <= #1 0;
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htim <= #1 0;
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vtim <= #1 0;
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vtim <= #1 0;
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hvlen <= #1 0;
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hvlen <= #1 0;
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VBARa <= #1 0;
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VBARa <= #1 0;
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| Line 222... |
Line 239... |
cursor0_ba <= #1 0;
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cursor0_ba <= #1 0;
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cursor1_xy <= #1 0;
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cursor1_xy <= #1 0;
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cursor1_ba <= #1 0;
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cursor1_ba <= #1 0;
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end
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end
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else if (reg_wacc)
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else if (reg_wacc)
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case (ADR_I) // synopsis full_case parallel_case
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case (adr_i) // synopsis full_case parallel_case
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HTIM_ADR : htim <= #1 DAT_I;
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HTIM_ADR : htim <= #1 dat_i;
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VTIM_ADR : vtim <= #1 DAT_I;
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VTIM_ADR : vtim <= #1 dat_i;
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HVLEN_ADR : hvlen <= #1 DAT_I;
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HVLEN_ADR : hvlen <= #1 dat_i;
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VBARA_ADR : VBARa <= #1 DAT_I[31: 2];
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VBARA_ADR : VBARa <= #1 dat_i[31: 2];
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VBARB_ADR : VBARb <= #1 DAT_I[31: 2];
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VBARB_ADR : VBARb <= #1 dat_i[31: 2];
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C0XY_ADR : cursor0_xy <= #1 DAT_I[31: 0];
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C0XY_ADR : cursor0_xy <= #1 dat_i[31: 0];
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C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];
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C0BAR_ADR : cursor0_ba <= #1 dat_i[31:11];
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C1XY_ADR : cursor1_xy <= #1 DAT_I[31: 0];
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C1XY_ADR : cursor1_xy <= #1 dat_i[31: 0];
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C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];
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C1BAR_ADR : cursor1_ba <= #1 dat_i[31:11];
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endcase
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endcase
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end
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end
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always@(posedge CLK_I)
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always@(posedge clk_i)
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begin
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begin
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cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);
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cursor0_ld <= #1 reg_wacc && (adr_i == C0BAR_ADR);
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cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);
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cursor1_ld <= #1 reg_wacc && (adr_i == C1BAR_ADR);
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end
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end
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// generate control register
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// generate control register
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always@(posedge CLK_I or negedge nRESET)
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always@(posedge clk_i or negedge arst_i)
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if (!nRESET)
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if (!arst_i)
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ctrl <= #1 0;
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ctrl <= #1 0;
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else if (RST_I)
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else if (rst_i)
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ctrl <= #1 0;
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ctrl <= #1 0;
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else if (reg_wacc & (REG_ADR == CTRL_ADR) )
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else if (reg_wacc & (REG_ADR == CTRL_ADR) )
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ctrl <= #1 DAT_I;
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ctrl <= #1 dat_i;
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else
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else
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begin
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begin
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ctrl[6] <= #1 ctrl[6] & !cbsint_in;
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ctrl[6] <= #1 ctrl[6] & !cbsint_in;
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ctrl[5] <= #1 ctrl[5] & !vbsint_in;
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ctrl[5] <= #1 ctrl[5] & !vbsint_in;
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end
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end
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// generate status register
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// generate status register
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always@(posedge CLK_I or negedge nRESET)
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always@(posedge clk_i or negedge arst_i)
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if (!nRESET)
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if (!arst_i)
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stat <= #1 0;
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stat <= #1 0;
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else if (RST_I)
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else if (rst_i)
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stat <= #1 0;
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stat <= #1 0;
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else
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else
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begin
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begin
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`ifdef VGA_HWC1
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`ifdef VGA_HWC1
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stat[21] <= #1 1'b1;
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stat[21] <= #1 1'b1;
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| Line 280... |
Line 297... |
stat[17] <= #1 acmp;
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stat[17] <= #1 acmp;
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stat[16] <= #1 avmp;
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stat[16] <= #1 avmp;
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|
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if (reg_wacc & (REG_ADR == STAT_ADR) )
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if (reg_wacc & (REG_ADR == STAT_ADR) )
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begin
|
begin
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stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
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stat[7] <= #1 cbsint_in | (stat[7] & !dat_i[7]);
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stat[6] <= #1 vbsint_in | (stat[6] & !DAT_I[6]);
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stat[6] <= #1 vbsint_in | (stat[6] & !dat_i[6]);
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stat[5] <= #1 hint_in | (stat[5] & !DAT_I[5]);
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stat[5] <= #1 hint_in | (stat[5] & !dat_i[5]);
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stat[4] <= #1 vint_in | (stat[4] & !DAT_I[4]);
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stat[4] <= #1 vint_in | (stat[4] & !dat_i[4]);
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stat[1] <= #1 luint_in | (stat[3] & !DAT_I[1]);
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stat[1] <= #1 luint_in | (stat[3] & !dat_i[1]);
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stat[0] <= #1 sint_in | (stat[0] & !DAT_I[0]);
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stat[0] <= #1 sint_in | (stat[0] & !dat_i[0]);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
stat[7] <= #1 stat[7] | cbsint_in;
|
stat[7] <= #1 stat[7] | cbsint_in;
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stat[6] <= #1 stat[6] | vbsint_in;
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stat[6] <= #1 stat[6] | vbsint_in;
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| Line 300... |
Line 317... |
end
|
end
|
end
|
end
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// decode control register
|
// decode control register
|
assign cursor1_en = ctrl[21];
|
assign cursor1_res = ctrl[25];
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assign cursor1_en = ctrl[24];
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assign cursor0_res = ctrl[23];
|
assign cursor0_en = ctrl[20];
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assign cursor0_en = ctrl[20];
|
assign bl = ctrl[15];
|
assign bl = ctrl[15];
|
assign csl = ctrl[14];
|
assign csl = ctrl[14];
|
assign vsl = ctrl[13];
|
assign vsl = ctrl[13];
|
assign hsl = ctrl[12];
|
assign hsl = ctrl[12];
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| Line 338... |
Line 357... |
assign Tvgdel = vtim[23:16];
|
assign Tvgdel = vtim[23:16];
|
assign Tvgate = vtim[15:0];
|
assign Tvgate = vtim[15:0];
|
assign Tvlen = hvlen[15:0];
|
assign Tvlen = hvlen[15:0];
|
|
|
|
|
|
`ifdef VGA_HWC0
|
|
// hookup cursor0 color registers
|
|
vga_cur_cregs cregs0(
|
|
.clk_i(clk_i),
|
|
.rst_i(rst_i),
|
|
.arst_i(arst_i),
|
|
.hsel_i(cc0_acc),
|
|
.hadr_i(adr_i[4:2]),
|
|
.hwe_i(we_i),
|
|
.hdat_i(dat_i),
|
|
.hdat_o(ccr0_dat_o), // host access
|
|
.hack_o(),
|
|
.cadr_i(cc0_adr_i),
|
|
.cdat_o(cc0_dat_o) // cursor processor access
|
|
);
|
|
`else
|
|
assign ccr0_dat_0 = 32'h0;
|
|
`endif
|
|
|
|
`ifdef VGA_HWC1
|
|
// hookup cursor1 color registers
|
|
vga_cur_cregs cregs1(
|
|
.clk_i(clk_i),
|
|
.rst_i(rst_i),
|
|
.arst_i(arst_i),
|
|
.hsel_i(cc1_acc),
|
|
.hadr_i(adr_i[4:2]),
|
|
.hwe_i(we_i),
|
|
.hdat_i(dat_i),
|
|
.hdat_o(ccr1_dat_o), // host access
|
|
.hack_o(),
|
|
.cadr_i(cc1_adr_i),
|
|
.cdat_o(cc1_dat_o) // cursor processor access
|
|
);
|
|
`else
|
|
assign ccr1_dat_o = 32'h0;
|
|
`endif
|
|
|
|
|
// assign output
|
// assign output
|
always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or
|
always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or
|
cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba)
|
cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba)
|
case (REG_ADR) // synopsis full_case parallel_case
|
casez (REG_ADR) // synopsis full_case parallel_case
|
CTRL_ADR : reg_dato = ctrl;
|
CTRL_ADR : reg_dato = ctrl;
|
STAT_ADR : reg_dato = stat;
|
STAT_ADR : reg_dato = stat;
|
HTIM_ADR : reg_dato = htim;
|
HTIM_ADR : reg_dato = htim;
|
VTIM_ADR : reg_dato = vtim;
|
VTIM_ADR : reg_dato = vtim;
|
HVLEN_ADR : reg_dato = hvlen;
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HVLEN_ADR : reg_dato = hvlen;
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VBARA_ADR : reg_dato = {VBARa, 2'b0};
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VBARA_ADR : reg_dato = {VBARa, 2'b0};
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VBARB_ADR : reg_dato = {VBARb, 2'b0};
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VBARB_ADR : reg_dato = {VBARb, 2'b0};
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C0XY_ADR : reg_dato = cursor0_xy;
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C0XY_ADR : reg_dato = cursor0_xy;
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C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
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C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
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CCR0_ADR : reg_dato = ccr0_dat_o;
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C1XY_ADR : reg_dato = cursor1_xy;
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C1XY_ADR : reg_dato = cursor1_xy;
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C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
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C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
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CCR1_ADR : reg_dato = ccr1_dat_o;
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default : reg_dato = 32'h0000_0000;
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default : reg_dato = 32'h0000_0000;
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endcase
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endcase
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always@(posedge CLK_I)
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always@(posedge clk_i)
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DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
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dat_o <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
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// generate interrupt request signal
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// generate interrupt request signal
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always@(posedge CLK_I)
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always@(posedge clk_i)
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INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
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inta_o <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
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endmodule
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endmodule
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