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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: vga_wb_slave.v,v 1.11 2002-04-20 10:02:39 rherveille Exp $
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// $Id: vga_wb_slave.v,v 1.12 2003-05-07 09:48:54 rherveille Exp $
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//
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//
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// $Date: 2002-04-20 10:02:39 $
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// $Date: 2003-05-07 09:48:54 $
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// $Revision: 1.11 $
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// $Revision: 1.12 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2002/04/20 10:02:39 rherveille
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// Changed video timing generator.
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// Changed wishbone master vertical gate count code.
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// Fixed a potential bug in the wishbone slave (cursor color register readout).
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//
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// Revision 1.10 2002/03/28 04:59:25 rherveille
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// Revision 1.10 2002/03/28 04:59:25 rherveille
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// Fixed two small bugs that only showed up when the hardware cursors were disabled
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// Fixed two small bugs that only showed up when the hardware cursors were disabled
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//
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//
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// Revision 1.9 2002/03/04 16:05:52 rherveille
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// Revision 1.9 2002/03/04 16:05:52 rherveille
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// Added hardware cursor support to wishbone master.
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// Added hardware cursor support to wishbone master.
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// Removed / Changed some strange logic constructions
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// Removed / Changed some strange logic constructions
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// Started work on hardware cursor support (not finished yet)
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// Started work on hardware cursor support (not finished yet)
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// Changed top-level name to vga_enh_top.v
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// Changed top-level name to vga_enh_top.v
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//
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//
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//synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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//synopsys translate_on
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`include "vga_defines.v"
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`include "vga_defines.v"
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module vga_wb_slave(clk_i, rst_i, arst_i, adr_i, dat_i, dat_o, sel_i, we_i, stb_i, cyc_i, ack_o, err_o, inta_o,
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module vga_wb_slave(
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bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
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clk_i, rst_i, arst_i, adr_i, dat_i, dat_o, sel_i, we_i, stb_i, cyc_i, ack_o, rty_o, err_o, inta_o,
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wbm_busy, dvi_odf, bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
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cursor0_res, cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_i, cc0_dat_o,
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cursor0_res, cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_i, cc0_dat_o,
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cursor1_res, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_i, cc1_dat_o,
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cursor1_res, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_i, cc1_dat_o,
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vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
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vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
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Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
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Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb,
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clut_acc, clut_ack, clut_q
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);
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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input we_i;
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input we_i;
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input stb_i;
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input stb_i;
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input cyc_i;
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input cyc_i;
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output ack_o;
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output ack_o;
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reg ack_o;
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reg ack_o;
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output rty_o;
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reg rty_o;
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output err_o;
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output err_o;
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reg err_o;
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reg err_o;
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output inta_o;
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output inta_o;
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reg inta_o;
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reg inta_o;
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// wishbone master controller feedback
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input wbm_busy; // data transfer in progress
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// control register settings
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// control register settings
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output [1:0] dvi_odf; // DVI output data format
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output bl; // blanking level
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output bl; // blanking level
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output csl; // composite sync level
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output csl; // composite sync level
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output vsl; // vsync level
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output vsl; // vsync level
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output hsl; // hsync level
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output hsl; // hsync level
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output pc; // pseudo color
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output pc; // pseudo color
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//
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//
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assign acc = cyc_i & stb_i;
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assign acc = cyc_i & stb_i;
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assign acc32 = (sel_i == 4'b1111);
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assign acc32 = (sel_i == 4'b1111);
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assign clut_acc = CLUT_ADR & acc & acc32;
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assign clut_acc = CLUT_ADR & acc & acc32;
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assign reg_acc = !CLUT_ADR & acc & acc32;
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assign reg_acc = ~CLUT_ADR & acc & acc32;
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assign reg_wacc = reg_acc & we_i;
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assign reg_wacc = reg_acc & we_i;
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assign cc0_acc = CCR0_ADR & acc & acc32;
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assign cc0_acc = (REG_ADR == CCR0_ADR) & acc & acc32;
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assign cc1_acc = CCR1_ADR & acc & acc32;
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assign cc1_acc = (REG_ADR == CCR1_ADR) & acc & acc32;
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always @(posedge clk_i)
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ack_o <= #1 ((reg_acc & acc32) | clut_ack) & ~(wbm_busy & REG_ADR == CTRL_ADR) & ~ack_o ;
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always@(posedge clk_i)
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always@(posedge clk_i)
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ack_o <= #1 ((reg_acc & acc32) | clut_ack) & !ack_o;
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rty_o <= #1 ((reg_acc & acc32) | clut_ack) & (wbm_busy & REG_ADR == CTRL_ADR) & ~rty_o ;
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always@(posedge clk_i)
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always@(posedge clk_i)
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err_o <= #1 acc & !acc32 & !err_o;
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err_o <= #1 acc & ~acc32 & ~err_o;
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// generate registers
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// generate registers
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always@(posedge clk_i or negedge arst_i)
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always@(posedge clk_i or negedge arst_i)
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begin : gen_regs
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begin : gen_regs
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always@(posedge clk_i or negedge arst_i)
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always@(posedge clk_i or negedge arst_i)
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if (!arst_i)
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if (!arst_i)
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ctrl <= #1 0;
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ctrl <= #1 0;
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else if (rst_i)
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else if (rst_i)
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ctrl <= #1 0;
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ctrl <= #1 0;
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else if (reg_wacc & (REG_ADR == CTRL_ADR) )
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else if (reg_wacc & (REG_ADR == CTRL_ADR) & ~wbm_busy )
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ctrl <= #1 dat_i;
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ctrl <= #1 dat_i;
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else
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else begin
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begin
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ctrl[6] <= #1 ctrl[6] & !cbsint_in;
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ctrl[6] <= #1 ctrl[6] & !cbsint_in;
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ctrl[5] <= #1 ctrl[5] & !vbsint_in;
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ctrl[5] <= #1 ctrl[5] & !vbsint_in;
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end
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end
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always@(posedge clk_i or negedge arst_i)
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always@(posedge clk_i or negedge arst_i)
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if (!arst_i)
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if (!arst_i)
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stat <= #1 0;
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stat <= #1 0;
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else if (rst_i)
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else if (rst_i)
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stat <= #1 0;
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stat <= #1 0;
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else
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else begin
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begin
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`ifdef VGA_HWC1
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`ifdef VGA_HWC1
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stat[21] <= #1 1'b1;
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stat[21] <= #1 1'b1;
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`else
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`else
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stat[21] <= #1 1'b0;
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stat[21] <= #1 1'b0;
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`endif
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`endif
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Line 344... |
end
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end
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end
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end
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// decode control register
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// decode control register
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assign dvi_odf = ctrl[29:28];
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assign cursor1_res = ctrl[25];
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assign cursor1_res = ctrl[25];
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assign cursor1_en = ctrl[24];
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assign cursor1_en = ctrl[24];
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assign cursor0_res = ctrl[23];
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assign cursor0_res = ctrl[23];
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assign cursor0_en = ctrl[20];
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assign cursor0_en = ctrl[20];
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assign bl = ctrl[15];
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assign bl = ctrl[15];
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