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Line 1... |
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--Mango DSP Ltd. Copyright (C) 2006
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--Creator: Nachum Kanovsky
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library ieee;
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use ieee.std_logic_1164.all;
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use work.design_top_constants.all;
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use std.textio.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity cpu_sim is
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port(
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fname : in filename;
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clk : out std_logic;
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rstN : out std_logic;
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cpu_cs1 : out std_logic;
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cpu_cs2 : out std_logic;
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cpu_cs3 : out std_logic;
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cpu_we : out std_logic;
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cpu_a : out std_logic_vector(4 downto 0);
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cpu_d : inout std_logic_vector(7 downto 0);
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cpu_irq4 : in std_logic;
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cpu_irq7 : in std_logic
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);
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end;
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architecture cpu_sim_simple of cpu_sim is
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signal sig_clk : std_logic := '0';
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shared variable tclk : time := 0 ns;
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shared variable rl : integer := 1;
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function to_lower (
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constant c : character)
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return character is
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begin -- to_lower
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if c >= 'A' and c <= 'Z' then
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return character'val(character'pos(c) - character'pos('A') + character'pos('a'));
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else
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return c;
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end if;
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end to_lower;
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procedure eat_white (
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variable l : inout line) is
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variable old_l : line := l;
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variable p : integer;
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begin
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if l = null then
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return;
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end if;
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if l'length = 0 then
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--string is empty
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deallocate(l);
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return;
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end if;
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p := l'left;
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while l'length > p - l'left and (l(p) = ' ' or l(p) = HT) loop
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p := p + 1;
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end loop;
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if p = l'left then
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--no whitespace
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return;
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elsif l'length <= p - l'left then
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--only whitespace - p passed the whole string
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deallocate(l);
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else
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l := new string'(old_l(p to old_l'right));
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deallocate(old_l);
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end if;
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end eat_white;
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procedure shrink_line (
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variable l : inout line;
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variable p : inout integer) is
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variable old_l : line := l;
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begin
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assert l /= null report "shrink_line l equals null" severity failure;
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if p = 0 then
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return;
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elsif p = l'length then
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deallocate(l);
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else
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l := new string'(old_l(old_l'left + p + 1 to old_l'right));
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deallocate(old_l);
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end if;
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end shrink_line;
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procedure read_word (
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l : inout line;
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value : inout line) is
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variable size : integer := 0;
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variable p : integer;
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begin
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if value /= null then
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deallocate(value);
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end if;
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eat_white(l);
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if l = null then
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return;
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end if;
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p := l'left;
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while l'length > p - l'left and (l(p) /= ' ' and l(p) /= HT) loop
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l(p) := to_lower(l(p));
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p := p + 1;
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end loop;
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p := p - 1;
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value := new string'(l(l'left to p));
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p := p + 1 - l'left;
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shrink_line(l, p);
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end read_word;
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procedure get_line(
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file f : text;
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variable l : inout line) is
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begin
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if l /= null then
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deallocate(l);
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end if;
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loop
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if endfile(f) then
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return;
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end if;
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readline(f, l);
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eat_white(l);
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if l /= null and l(l'left) /= '#' then
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return;
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else
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deallocate(l);
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end if;
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end loop;
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end get_line;
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type dfile is record
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fn : line;
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ln : integer;
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end record;
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type dfile_access is access dfile;
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procedure readline(
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variable dfa : inout dfile_access;
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l : inout line) is
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file fl : text;
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variable c : integer := 0;
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begin
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file_open(fl, dfa.fn.all, read_mode);
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if l /= null then
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deallocate(l);
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end if;
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while c /= dfa.ln loop
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if endfile(fl) then
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if l /= null then
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deallocate(l);
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end if;
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file_close(fl);
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return;
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end if;
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readline(fl, l);
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c := c + 1;
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end loop;
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if endfile(fl) then
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if l /= null then
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deallocate(l);
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end if;
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file_close(fl);
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return;
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end if;
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readline(fl, l);
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file_close(fl);
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dfa.ln := dfa.ln + 1;
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end readline;
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--writeline deallocates the line
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procedure write(
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variable fn : in line;
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variable l : inout line) is
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file fl : text;
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file fl_tmp : text;
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variable l_tmp : line;
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begin
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file_open(fl_tmp, "tmp.txt", write_mode);
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file_open(fl, fn.all, read_mode);
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while not endfile(fl) loop
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readline(fl, l_tmp);
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writeline(fl_tmp, l_tmp);
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end loop;
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l_tmp := new string'(l(l'left to l'right));
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writeline(fl_tmp, l_tmp);
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file_close(fl_tmp);
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file_close(fl);
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file_open(fl_tmp, "tmp.txt", read_mode);
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file_open(fl, fn.all, write_mode);
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while not endfile(fl_tmp) loop
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readline(fl_tmp, l_tmp);
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writeline(fl, l_tmp);
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end loop;
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file_close(fl_tmp);
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file_close(fl);
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end write;
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procedure write(
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variable fn : in line;
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variable sl : in std_logic) is
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file fl : text;
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file fl_tmp : text;
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variable b : bit;
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variable l_tmp : line;
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begin
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file_open(fl_tmp, "tmp.txt", write_mode);
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file_open(fl, fn.all, read_mode);
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while not endfile(fl) loop
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readline(fl, l_tmp);
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writeline(fl_tmp, l_tmp);
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end loop;
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if sl = '1' then
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b := '1';
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else
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b := '0';
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end if;
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write(l_tmp, b);
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writeline(fl, l_tmp);
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file_close(fl_tmp);
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file_close(fl);
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file_open(fl_tmp, "tmp.txt", read_mode);
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file_open(fl, fn.all, write_mode);
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while not endfile(fl_tmp) loop
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readline(fl_tmp, l_tmp);
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writeline(fl, l_tmp);
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end loop;
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file_close(fl_tmp);
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file_close(fl);
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end write;
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procedure write(
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variable fn : in line;
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variable slv8 : in std_logic_vector(7 downto 0)) is
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file fl : text;
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file fl_tmp : text;
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variable l_tmp : line;
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begin
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file_open(fl_tmp, "tmp.txt", write_mode);
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file_open(fl, fn.all, read_mode);
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while not endfile(fl) loop
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readline(fl, l_tmp);
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writeline(fl_tmp, l_tmp);
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end loop;
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write(l_tmp, to_bitVector(slv8));
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writeline(fl_tmp, l_tmp);
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file_close(fl_tmp);
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file_close(fl);
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file_open(fl_tmp, "tmp.txt", read_mode);
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file_open(fl, fn.all, write_mode);
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while not endfile(fl_tmp) loop
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readline(fl_tmp, l_tmp);
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writeline(fl, l_tmp);
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end loop;
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file_close(fl_tmp);
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file_close(fl);
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end write;
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procedure get_line(
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variable dfa : inout dfile_access;
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variable l : inout line) is
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variable l_temp : line;
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begin
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if l /= null then
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deallocate(l);
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end if;
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loop
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readline(dfa, l_temp);
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if l_temp = null then
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l := null;
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return;
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end if;
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eat_white(l_temp);
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if l_temp /= null and l_temp(l_temp'left) /= '#' then
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l := l_temp;
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return;
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end if;
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end loop;
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end get_line;
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type wait_commands is (wt_done, wt_time, wt_irq4, wt_irq7);
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type waiter is record
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cmd : wait_commands;
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tm_end : time;
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v : std_logic;
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end record;
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type waiter_access is access waiter;
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procedure check_wait(
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variable w : inout waiter) is
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begin
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case w.cmd is
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when wt_time =>
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if now >= w.tm_end then
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w.cmd := wt_done;
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end if;
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when wt_irq4 =>
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if cpu_irq4 = w.v then
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w.cmd := wt_done;
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end if;
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when wt_irq7 =>
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if cpu_irq7 = w.v then
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w.cmd := wt_done;
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end if;
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when others => null;
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end case;
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end check_wait;
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type var_types is (vt_string, vt_bit, vt_vector8);
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type var;
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type var_access is access var;
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type var_accessx16 is array (15 downto 0) of var_access;
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type var is record
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n : line;
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vt : var_types;
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s : line;
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sl : std_logic;
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slv8 : std_logic_vector(7 downto 0);
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end record;
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type vars;
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type vars_access is access vars;
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type vars is record
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va16 : var_accessx16;
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next_vsa : vars_access;
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end record;
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procedure get_var(
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variable n : in line;
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variable vsa : in vars_access;
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variable va : out var_access) is
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begin
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if vsa = null then
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return;
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end if;
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va := null;
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for i in vsa.va16'range loop
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if vsa.va16(i) /= null and vsa.va16(i).n.all = n.all then
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va := vsa.va16(i);
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return;
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end if;
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end loop;
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get_var(n, vsa.next_vsa, va);
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end get_var;
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procedure add_var(
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variable vsa : inout vars_access;
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variable n : in line;
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variable vt : in var_types) is
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variable vsa_temp : vars_access;
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variable v_temp : var_access;
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begin
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vsa_temp := vsa.next_vsa;
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vsa.next_vsa := null;
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get_var(n, vsa, v_temp);
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vsa.next_vsa := vsa_temp;
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vsa_temp := null;
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if v_temp /= null then
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return;
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end if;
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for i in vsa.va16'range loop
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if vsa.va16(i) = null then
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vsa.va16(i) := new var;
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vsa.va16(i).n := new string'(n(n'left to n'right));
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vsa.va16(i).vt := vt;
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return;
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end if;
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end loop;
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report "too many variables" severity failure;
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end add_var;
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procedure add_var(
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variable vsa : inout vars_access;
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variable n : in line;
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variable s : in line) is
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variable v_temp : var_access;
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variable vt : var_types;
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begin
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vt := vt_string;
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add_var(vsa, n, vt);
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get_var(n, vsa, v_temp);
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v_temp.s := new string'(s(s'left to s'right));
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end add_var;
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procedure add_var(
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variable vsa : inout vars_access;
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variable n : in line;
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variable sl : in std_logic) is
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variable v_temp : var_access;
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variable vt : var_types;
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begin
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vt := vt_string;
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add_var(vsa, n, vt);
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get_var(n, vsa, v_temp);
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v_temp.sl := sl;
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end add_var;
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procedure add_var(
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variable vsa : inout vars_access;
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variable n : in line;
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variable slv8 : in std_logic_vector(7 downto 0)) is
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variable v_temp : var_access;
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variable vt : var_types;
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begin
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vt := vt_string;
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add_var(vsa, n, vt);
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get_var(n, vsa, v_temp);
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v_temp.slv8 := slv8;
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end add_var;
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type thread_states is (st_ready, st_done);
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type thread;
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type thread_access is access thread;
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type thread is record
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dfa : dfile_access;
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ln_start : integer;
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st : thread_states;
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w : waiter_access;
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vsa : vars_access;
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next_tha : thread_access;
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end record;
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type tholder;
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type tholder_access is access tholder;
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type tholder is record
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th : thread_access;
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n : tholder_access;
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p : tholder_access;
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end record;
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procedure init_thread (
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variable tha : inout thread_access;
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variable dfa : in dfile_access;
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variable ln : in integer;
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variable w : in waiter_access;
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variable vsa : in vars_access) is
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variable int : integer;
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begin
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tha.dfa := dfa;
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tha.ln_start := ln;
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tha.st := st_ready;
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tha.w := w;
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tha.vsa := new vars;
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tha.vsa.next_vsa := vsa;
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tha.w.cmd := wt_done;
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end init_thread;
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procedure declare_var(
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variable l_type : inout line;
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variable l_varname : inout line;
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variable vsa : inout vars_access) is
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variable vt : var_types;
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begin
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assert l_type /= null and l_varname /= null report "declare_var bad parameters" severity failure;
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if l_type.all = "bit" then
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vt := vt_bit;
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add_var(vsa, l_varname, vt);
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elsif l_type.all = "vector8" then
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vt := vt_vector8;
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add_var(vsa, l_varname, vt);
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elsif l_type.all = "string" then
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vt := vt_string;
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add_var(vsa, l_varname, vt);
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else
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report "l_type is not bit, vector8, or string" severity failure;
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end if;
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end declare_var;
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procedure var_test(
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variable l_left : inout line;
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variable l_op : inout line;
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variable l_right : inout line;
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variable bl_good : inout boolean;
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variable vsa : inout vars_access) is
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variable va_left : var_access;
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variable va_right : var_access;
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variable sl : std_logic;
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variable slv8 : std_logic_vector(7 downto 0);
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variable b : bit;
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variable bv8 : bit_vector(7 downto 0);
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variable s : line;
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begin
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assert l_left /= null and l_op /= null and l_right /= null report "var_test invalid null parameters" severity failure;
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get_var(l_left, vsa, va_left);
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assert va_left /= null report "var_test left variable not found" severity failure;
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get_var(l_right, vsa, va_right);
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if va_right /= null then
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assert va_left.vt = va_right.vt report "var_test var types not the same" severity failure;
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case va_right.vt is
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when vt_bit =>
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sl := va_right.sl;
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when vt_vector8 =>
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slv8 := va_right.slv8;
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when vt_string =>
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s := va_right.s;
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end case;
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else
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case va_left.vt is
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when vt_bit =>
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read(l_right, b, bl_good);
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assert bl_good = true report "var_test last parameter failed read" severity failure;
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if b = '1' then
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sl := '1';
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else
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sl := '0';
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end if;
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when vt_vector8 =>
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read(l_right, bv8, bl_good);
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assert bl_good = true report "var_test last parameter failed read" severity failure;
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slv8 := to_stdlogicvector(bv8);
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when vt_string =>
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s := l_right;
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end case;
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end if;
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bl_good := false;
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case va_left.vt is
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when vt_bit =>
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assert l_op.all = "==" or l_op.all = ">" or l_op.all = "<" or l_op.all = "&" or l_op.all = "|" report "var_test invalid operation for bit, use ==,>,<,&,|" severity failure;
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if l_op.all = "==" then
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if va_left.sl = sl then
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bl_good := true;
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return;
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end if;
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elsif l_op.all = ">" then
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if va_left.sl > sl then
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bl_good := true;
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return;
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end if;
|
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elsif l_op.all = "<" then
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if va_left.sl < sl then
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bl_good := true;
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return;
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end if;
|
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elsif l_op.all = "&" then
|
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if (va_left.sl and sl) /= '0' then
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bl_good := true;
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return;
|
|
end if;
|
|
elsif l_op.all = "|" then
|
|
if (va_left.sl or sl) /= '0' then
|
|
bl_good := true;
|
|
return;
|
|
end if;
|
|
end if;
|
|
when vt_vector8 =>
|
|
assert l_op.all = "==" or l_op.all = ">" or l_op.all = "<" or l_op.all = "&" or l_op.all = "|" report "var_test invalid operation for vector8, use ==,>,<,&,|" severity failure;
|
|
if l_op.all = "==" then
|
|
if va_left.slv8 = slv8 then
|
|
bl_good := true;
|
|
return;
|
|
end if;
|
|
elsif l_op.all = ">" then
|
|
if va_left.slv8 > slv8 then
|
|
bl_good := true;
|
|
return;
|
|
end if;
|
|
elsif l_op.all = "<" then
|
|
if va_left.slv8 < slv8 then
|
|
bl_good := true;
|
|
return;
|
|
end if;
|
|
elsif l_op.all = "&" then
|
|
if (va_left.slv8 and slv8) /= "00000000" then
|
|
bl_good := true;
|
|
return;
|
|
end if;
|
|
elsif l_op.all = "|" then
|
|
if (va_left.slv8 or slv8) /= "00000000" then
|
|
bl_good := true;
|
|
return;
|
|
end if;
|
|
end if;
|
|
when vt_string =>
|
|
assert l_op.all = "==" report "var_test string has only == operation" severity failure;
|
|
if va_left.s = s then
|
|
bl_good := true;
|
|
return;
|
|
end if;
|
|
when others => null;
|
|
end case;
|
|
end var_test;
|
|
|
|
--variables are deallocated in this function
|
|
procedure var_op (
|
|
variable l_left : inout line;
|
|
variable l_op : inout line;
|
|
variable l_right : inout line;
|
|
variable vsa : inout vars_access) is
|
|
variable va_left : var_access;
|
|
variable va_right : var_access;
|
|
variable slv8 : std_logic_vector(7 downto 0);
|
|
variable slv16 : std_logic_vector(15 downto 0);
|
|
variable b : bit;
|
|
variable bv8 : bit_vector(7 downto 0);
|
|
variable bl_good : boolean;
|
|
begin
|
|
assert l_left /= null and l_op /= null and l_right /= null report "l_left or l_op or l_right are null" severity failure;
|
|
if l_left.all = "bit" or l_left.all = "vector8" or l_left.all = "string" then
|
|
declare_var(l_left, l_op, vsa);
|
|
l_left := l_op;
|
|
l_op := null;
|
|
read_word(l_right, l_op);
|
|
end if;
|
|
get_var(l_left, vsa, va_left);
|
|
assert va_left /= null report "variable not found" severity failure;
|
|
case va_left.vt is
|
|
when vt_string =>
|
|
assert l_op.all = "=" report "illegal op, string has only = operation" severity failure;
|
|
if va_left.s /= null then
|
|
deallocate(va_left.s);
|
|
end if;
|
|
get_var(l_right, vsa, va_right);
|
|
if va_right /= null then
|
|
va_left.s := new string'(va_right.s(va_right.s'left to va_right.s'right));
|
|
else
|
|
read_word(l_right, va_left.s);
|
|
end if;
|
|
when vt_bit =>
|
|
assert l_op.all = "=" report "illegal op, bit has only = operation" severity failure;
|
|
get_var(l_right, vsa, va_right);
|
|
if va_right /= null then
|
|
assert va_right.vt = vt_bit report "non bit variable being op'ed with bit variable" severity failure;
|
|
va_left.sl := va_right.sl;
|
|
else
|
|
read(l_right, b, bl_good);
|
|
if bl_good = true then
|
|
if b = '1' then
|
|
va_left.sl := '1';
|
|
else
|
|
va_left.sl := '0';
|
|
end if;
|
|
else
|
|
report "bit operation missing bit value" severity failure;
|
|
end if;
|
|
end if;
|
|
when vt_vector8 =>
|
|
get_var(l_right, vsa, va_right);
|
|
if va_right /= null then
|
|
assert va_right.vt = vt_vector8 report "non vector8 variable being op'ed with vector8 variable" severity failure;
|
|
slv8 := va_right.slv8;
|
|
else
|
|
read(l_right, bv8);
|
|
slv8 := to_stdlogicvector(bv8);
|
|
end if;
|
|
if l_op.all = "=" then
|
|
va_left.slv8 := slv8;
|
|
elsif l_op.all = "+=" then
|
|
va_left.slv8 := va_left.slv8 + slv8;
|
|
elsif l_op.all = "-=" then
|
|
va_left.slv8 := va_left.slv8 - slv8;
|
|
elsif l_op.all = "*=" then
|
|
slv16 := va_left.slv8 * slv8;
|
|
va_left.slv8 := slv16(7 downto 0);
|
|
elsif l_op.all = "&=" then
|
|
va_left.slv8 := va_left.slv8 and slv8;
|
|
elsif l_op.all = "|=" then
|
|
va_left.slv8 := va_left.slv8 or slv8;
|
|
else
|
|
report "illegal op, vector8 has only =, +, -, &, | operations" severity failure;
|
|
end if;
|
|
end case;
|
|
deallocate(l_left);
|
|
deallocate(l_op);
|
|
deallocate(l_right);
|
|
end var_op;
|
|
|
|
procedure clear(
|
|
variable fn : inout line) is
|
|
file fl : text;
|
|
begin
|
|
file_open(fl, fn.all, write_mode);
|
|
file_close(fl);
|
|
end clear;
|
|
|
|
procedure find_match (
|
|
variable dfa : inout dfile_access;
|
|
constant s_open : in string;
|
|
constant s_close : in string) is
|
|
variable l : line;
|
|
variable cmd : line;
|
|
begin
|
|
get_line(dfa, l);
|
|
read_word(l, cmd);
|
|
while cmd.all /= s_close loop
|
|
if cmd.all = s_open then
|
|
find_match(dfa, s_open, s_close);
|
|
end if;
|
|
get_line(dfa, l);
|
|
read_word(l, cmd);
|
|
end loop;
|
|
end find_match;
|
|
|
|
procedure find_match (
|
|
variable dfa : inout dfile_access;
|
|
constant s_open : in string;
|
|
constant s_other : in string;
|
|
constant s_close : in string) is
|
|
variable l : line;
|
|
variable cmd : line;
|
|
begin
|
|
get_line(dfa, l);
|
|
read_word(l, cmd);
|
|
while cmd.all /= s_close and cmd.all /= s_other loop
|
|
if cmd.all = s_open then
|
|
find_match(dfa, s_open, s_close);
|
|
end if;
|
|
get_line(dfa, l);
|
|
read_word(l, cmd);
|
|
end loop;
|
|
end find_match;
|
|
|
|
procedure read_dma (
|
|
variable l : inout line;
|
|
variable vsa : inout vars_access;
|
|
signal cpu_cs1 : out std_logic;
|
|
signal cpu_we : out std_logic;
|
|
signal cpu_a : out std_logic_vector(4 downto 0);
|
|
signal cpu_d : inout std_logic_vector(7 downto 0)) is
|
|
variable l_tmp : line;
|
|
variable va : var_access;
|
|
variable addr : std_logic_vector(7 downto 0);
|
|
variable size : integer;
|
|
variable incr : integer;
|
|
variable bl_good : boolean;
|
|
variable bv8 : bit_vector(7 downto 0);
|
|
variable filename : line;
|
|
variable slv8 : std_logic_vector(7 downto 0);
|
|
begin
|
|
read_word(l, l_tmp);
|
|
assert l_tmp /= null report "read_dma parameter missing" severity failure;
|
|
get_var(l_tmp, vsa, va);
|
|
if va = null then
|
|
read(l_tmp, bv8, bl_good);
|
|
assert bl_good report "read_dma address invalid" severity failure;
|
|
addr := to_stdlogicvector(bv8);
|
|
else
|
|
assert va.vt = vt_vector8 report "read_dma address variable not found" severity failure;
|
|
addr := va.slv8;
|
|
end if;
|
|
read_word(l, l_tmp);
|
|
assert l_tmp /= null report "read_dma parameter missing" severity failure;
|
|
get_var(l_tmp, vsa, va);
|
|
if va = null then
|
|
read(l_tmp, bv8, bl_good);
|
|
assert bl_good report "read_dma size invalid" severity failure;
|
|
size := to_integer(unsigned(to_stdlogicvector(bv8)));
|
|
else
|
|
assert va /= null and va.vt = vt_vector8 report "read_dma size variable not found" severity failure;
|
|
size := to_integer(unsigned(va.slv8));
|
|
end if;
|
|
read_word(l, l_tmp);
|
|
assert l_tmp /= null report "read_dma parameter missing" severity failure;
|
|
get_var(l_tmp, vsa, va);
|
|
if va = null then
|
|
read(l_tmp, bv8, bl_good);
|
|
assert bl_good report "read_dma incr invalid" severity failure;
|
|
incr := to_integer(unsigned(to_stdlogicvector(bv8)));
|
|
else
|
|
assert va /= null and va.vt = vt_vector8 report "read_dma incr variable not found" severity failure;
|
|
incr := to_integer(unsigned(va.slv8));
|
|
end if;
|
|
read_word(l, l_tmp);
|
|
assert l_tmp /= null report "read_dma parameter missing" severity failure;
|
|
filename := l_tmp;
|
|
l_tmp := null;
|
|
|
|
for i in 0 to size - 1 loop
|
|
if i < (size + rl) then
|
|
cpu_cs1 <= '1';
|
|
cpu_a <= addr(cpu_a'range);
|
|
addr := addr + incr;
|
|
end if;
|
|
if i > rl then
|
|
slv8 := cpu_d;
|
|
write(filename, slv8);
|
|
end if;
|
|
wait for 1 ps;
|
|
wait until rising_edge(sig_clk);
|
|
end loop;
|
|
cpu_cs1 <= '0';
|
|
cpu_a <= (others => '0');
|
|
for i in 0 to rl - 1 loop
|
|
if (size + i) > rl then
|
|
slv8 := cpu_d;
|
|
write(filename, slv8);
|
|
end if;
|
|
wait for 1 ps;
|
|
wait until rising_edge(sig_clk);
|
|
end loop;
|
|
slv8 := cpu_d;
|
|
write(filename, slv8);
|
|
-- cpu_cs1 <= '1';
|
|
-- wait for 1 ps;
|
|
-- wait until rising_edge(sig_clk);
|
|
-- cpu_cs1 <= '0';
|
|
-- cpu_a <= (others => '0');
|
|
-- for i in 1 to rl loop
|
|
-- --waiting for data to get back
|
|
-- wait for 1 ps;
|
|
-- wait until rising_edge(sig_clk);
|
|
-- end loop; -- i
|
|
-- read_word(l, l_first);
|
|
-- if l_first = null then
|
|
-- exit;
|
|
-- end if;
|
|
-- get_var(l_first, tha.vsa, va);
|
|
-- assert va /= null and va.vt = vt_vector8 report "illegal address for read" severity failure;
|
|
-- va.slv8 := cpu_d;
|
|
-- va := null;
|
|
end read_dma;
|
|
|
|
procedure process_thread (
|
|
variable tha : inout thread_access;
|
|
signal cpu_cs1 : out std_logic;
|
|
signal cpu_we : out std_logic;
|
|
signal cpu_a : out std_logic_vector(4 downto 0);
|
|
signal cpu_d : inout std_logic_vector(7 downto 0)) is
|
|
variable va : var_access;
|
|
variable l : line;
|
|
variable tm : time;
|
|
variable b : bit;
|
|
variable l_first : line;
|
|
variable l_second : line;
|
|
variable bl_good : boolean;
|
|
variable bv8 : bit_vector(7 downto 0);
|
|
begin
|
|
while tha.st = st_ready and tha.w.all.cmd = wt_done loop
|
|
if tha.next_tha /= null then
|
|
if tha.next_tha.st = st_done then
|
|
find_match(tha.dfa, "while", "while_end");
|
|
deallocate(tha.next_tha);
|
|
else
|
|
process_thread(tha.next_tha, cpu_cs1, cpu_we, cpu_a, cpu_d);
|
|
exit;
|
|
end if;
|
|
end if;
|
|
if tha.st = st_ready then
|
|
get_line(tha.dfa, l);
|
|
read_word(l, l_first);
|
|
end if;
|
|
tha.st := st_ready;
|
|
if l_first = null then
|
|
tha.st := st_done;
|
|
elsif l_first.all = "wait" then
|
|
read(l, tm);
|
|
tha.w.cmd := wt_time;
|
|
tha.w.tm_end := tm + now;
|
|
check_wait(tha.w.all);
|
|
elsif l_first.all = "wait_interrupt4" then
|
|
tha.w.cmd := wt_irq4;
|
|
read(l, b, bl_good);
|
|
if bl_good then
|
|
if b = '1' then
|
|
tha.w.v := '1';
|
|
else
|
|
tha.w.v := '0';
|
|
end if;
|
|
else
|
|
tha.w.v := '1';
|
|
end if;
|
|
check_wait(tha.w.all);
|
|
elsif l_first.all = "while" then
|
|
tha.next_tha := new thread;
|
|
init_thread(tha.next_tha, tha.dfa, tha.dfa.ln, tha.w, tha.vsa);
|
|
elsif l_first.all = "while_exit" then
|
|
tha.st := st_done;
|
|
elsif l_first.all = "while_end" then
|
|
tha.dfa.ln := tha.ln_start;
|
|
elsif l_first.all = "if" then
|
|
read_word(l, l_first);
|
|
read_word(l, l_second);
|
|
var_test(l_first, l_second, l, bl_good, tha.vsa);
|
|
if bl_good = false then
|
|
find_match(tha.dfa, "if", "if_else", "if_end");
|
|
end if;
|
|
elsif l_first.all = "if_else" then
|
|
find_match(tha.dfa, "if", "if_end");
|
|
elsif l_first.all = "if_end" then
|
|
elsif l_first.all = "clear" then
|
|
read_word(l, l_first);
|
|
assert l_first /= null report "clear without file or variable name" severity failure;
|
|
get_var(l_first, tha.vsa, va);
|
|
if va /= null then
|
|
assert va.vt = vt_string report "non string variable name" severity failure;
|
|
clear(va.s);
|
|
else
|
|
clear(l_first);
|
|
end if;
|
|
deallocate(l_first);
|
|
va := null;
|
|
elsif l_first.all = "read" then
|
|
cpu_cs1 <= '1';
|
|
read_word(l, l_first);
|
|
assert l_first /= null report "read parameter missing" severity failure;
|
|
get_var(l_first, tha.vsa, va);
|
|
assert va = null or va.vt = vt_vector8 report "illegal address for read" severity failure;
|
|
if va = null then
|
|
read(l_first, bv8);
|
|
cpu_a <= to_stdlogicvector(bv8)(cpu_a'left downto 0);
|
|
else
|
|
cpu_a <= va.slv8(cpu_a'left downto 0);
|
|
va := null;
|
|
end if;
|
|
--waiting for request to get to cpu block
|
|
wait for 1 ps;
|
|
wait until rising_edge(sig_clk);
|
|
cpu_cs1 <= '0';
|
|
cpu_a <= (others => '0');
|
|
for i in 1 to rl loop
|
|
--waiting for data to get back
|
|
wait for 1 ps;
|
|
wait until rising_edge(sig_clk);
|
|
end loop; -- i
|
|
read_word(l, l_first);
|
|
if l_first = null then
|
|
exit;
|
|
end if;
|
|
get_var(l_first, tha.vsa, va);
|
|
assert va /= null and va.vt = vt_vector8 report "illegal address for read" severity failure;
|
|
va.slv8 := cpu_d;
|
|
va := null;
|
|
elsif l_first.all = "write" then
|
|
cpu_cs1 <= '1';
|
|
cpu_we <= '1';
|
|
read_word(l, l_first);
|
|
assert l_first /= null report "write parameter missing" severity failure;
|
|
get_var(l_first, tha.vsa, va);
|
|
assert va = null or va.vt = vt_vector8 report "illegal address for write" severity failure;
|
|
if va = null then
|
|
read(l_first, bv8);
|
|
cpu_a <= to_stdlogicvector(bv8)(cpu_a'left downto 0);
|
|
else
|
|
cpu_a <= va.slv8(cpu_a'left downto 0);
|
|
va := null;
|
|
end if;
|
|
deallocate(l_first);
|
|
read_word(l, l_first);
|
|
assert l_first /= null report "write parameter missing" severity failure;
|
|
get_var(l_first, tha.vsa, va);
|
|
assert va = null or va.vt = vt_vector8 report "illegal data for write" severity failure;
|
|
if va = null then
|
|
read(l_first, bv8);
|
|
cpu_d <= to_stdlogicvector(bv8)(cpu_d'left downto 0);
|
|
else
|
|
cpu_d <= va.slv8(cpu_d'left downto 0);
|
|
va := null;
|
|
end if;
|
|
deallocate(l_first);
|
|
wait for 1 ps;
|
|
wait until rising_edge(sig_clk);
|
|
cpu_cs1 <= '0';
|
|
cpu_we <= '0';
|
|
cpu_a <= (others => '0');
|
|
cpu_d <= (others => 'Z');
|
|
elsif l_first.all = "read_dma" then
|
|
read_dma(l, tha.vsa, cpu_cs1, cpu_we, cpu_a, cpu_d);
|
|
elsif l_first.all = "write" then
|
|
-- write_dma(l, tha.vsa, cpu_cs1, cpu_we, cpu_a, cpu_d);
|
|
elsif l_first.all = "print" then
|
|
read_word(l, l_first);
|
|
assert l_first /= null report "no file or variable name for print" severity failure;
|
|
get_var(l_first, tha.vsa, va);
|
|
if va /= null then
|
|
deallocate(l_first);
|
|
l_first := va.s;
|
|
va := null;
|
|
end if;
|
|
read_word(l, l_second);
|
|
assert l_second /= null report "no variable name for print" severity failure;
|
|
get_var(l_second, tha.vsa, va);
|
|
l_second := null;
|
|
assert va /= null report "invalid variable for print" severity failure;
|
|
if va.vt = vt_string then
|
|
write(l_first, va.s);
|
|
elsif va.vt = vt_bit then
|
|
write(l_first, va.sl);
|
|
elsif va.vt = vt_vector8 then
|
|
write(l_first, va.slv8);
|
|
end if;
|
|
l_first := null;
|
|
va := null;
|
|
elsif l_first.all = "breakpoint" then
|
|
deallocate(l_first);
|
|
else
|
|
read_word(l, l_second);
|
|
var_op(l_first, l_second, l, tha.vsa);
|
|
end if;
|
|
end loop;
|
|
deallocate(l);
|
|
deallocate(l_first);
|
|
end process_thread;
|
|
|
|
begin
|
|
sig_clk <= not sig_clk after tclk;
|
|
clk <= sig_clk;
|
|
process
|
|
file fl : text;
|
|
variable l : line;
|
|
variable l_params : line;
|
|
variable tm : time;
|
|
variable bl_alldone : boolean;
|
|
variable vsa : vars_access;
|
|
variable l_first : line;
|
|
variable l_second : line;
|
|
variable l_third : line;
|
|
variable wa : waiter_access;
|
|
variable dfa : dfile_access;
|
|
variable tholda_start : tholder_access;
|
|
variable tholda : tholder_access;
|
|
variable tholda_prev : tholder_access;
|
|
begin
|
|
rstN <= '0';
|
|
cpu_cs1 <= '0';
|
|
cpu_cs2 <= '0';
|
|
cpu_cs3 <= '0';
|
|
cpu_we <= '0';
|
|
cpu_a <= (others => '0');
|
|
cpu_d <= (others => 'Z');
|
|
file_open(fl, fname, read_mode);
|
|
vsa := new vars;
|
|
loop
|
|
get_line(fl, l);
|
|
read_word(l, l_first);
|
|
if l_first = null then
|
|
exit;
|
|
elsif l_first.all = "clock" then
|
|
read(l, tm);
|
|
tclk := tm;
|
|
elsif l_first.all = "reset" then
|
|
read(l, tm);
|
|
wait for tm;
|
|
rstN <= '1';
|
|
elsif l_first.all = "read_latency" then
|
|
read(l, rl);
|
|
elsif l_first.all = "thread" then
|
|
tholda := new tholder;
|
|
if tholda_start = null then
|
|
tholda_start := tholda;
|
|
tholda_prev := tholda_start;
|
|
else
|
|
tholda_prev.n := tholda;
|
|
tholda_prev := tholda;
|
|
end if;
|
|
tholda.th := new thread;
|
|
read_word(l, l_second);
|
|
wa := new waiter;
|
|
dfa := new dfile;
|
|
dfa.fn := l_second;
|
|
l_second := null;
|
|
dfa.ln := 0;
|
|
init_thread(tholda.th, dfa, dfa.ln, wa, vsa);
|
|
while l_first /= null and l_first.all /= "parameters" loop
|
|
get_line(tholda.th.dfa, l_params);
|
|
read_word(l_params, l_first);
|
|
end loop;
|
|
if l_first /= null and l_first.all = "parameters" then
|
|
loop
|
|
read_word(l_params, l_first);
|
|
if l_first = null then
|
|
exit;
|
|
end if;
|
|
assert l_first.all = "bit" or l_first.all = "vector8" or l_first.all = "string" report "illegal variable type in parameter list" severity failure;
|
|
read_word(l_params, l_second);
|
|
assert l_second /= null report "variable name missing in parameter list" severity failure;
|
|
declare_var(l_first, l_second, tholda.th.vsa);
|
|
deallocate(l_first);
|
|
l_first := l_second;
|
|
l_second := new string'("=");
|
|
read_word(l, l_third);
|
|
assert l_third /= null report "variable value missing in thread spawn call" severity failure;
|
|
var_op(l_first, l_second, l_third, tholda.th.vsa);
|
|
end loop;
|
|
else
|
|
tholda.th.dfa.ln := 0;
|
|
end if;
|
|
tholda := tholda.n;
|
|
else
|
|
read_word(l, l_second);
|
|
var_op(l_first, l_second, l, vsa);
|
|
end if;
|
|
end loop;
|
|
wait for 1 ps;
|
|
wait until rising_edge(sig_clk);
|
|
loop
|
|
bl_alldone := true;
|
|
tholda := tholda_start;
|
|
while tholda /= null loop
|
|
if tholda.th.w.cmd /= wt_done then
|
|
check_wait(tholda.th.w.all);
|
|
bl_alldone := false;
|
|
end if;
|
|
tholda := tholda.n;
|
|
end loop;
|
|
tholda := tholda_start;
|
|
tholda_prev := null;
|
|
while tholda /= null loop
|
|
if tholda.th.w.cmd = wt_done then
|
|
process_thread(tholda.th, cpu_cs1, cpu_we, cpu_a, cpu_d);
|
|
bl_alldone := false;
|
|
end if;
|
|
if tholda.th.st = st_done then
|
|
if tholda_prev /= null then
|
|
tholda_prev.n := tholda.n;
|
|
else
|
|
tholda_start := tholda.n;
|
|
end if;
|
|
deallocate(tholda.th.w);
|
|
deallocate(tholda.th.vsa);
|
|
deallocate(tholda.th.dfa);
|
|
deallocate(tholda.th);
|
|
end if;
|
|
tholda_prev := tholda;
|
|
tholda := tholda.n;
|
|
end loop;
|
|
wait for 1 ps;
|
|
wait until rising_edge(sig_clk);
|
|
if bl_alldone then
|
|
cpu_cs1 <= '0';
|
|
cpu_we <= '0';
|
|
cpu_a <= (others => '0');
|
|
cpu_d <= (others => 'Z');
|
|
wait;
|
|
end if;
|
|
end loop;
|
|
end process;
|
|
end cpu_sim_simple;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
