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https://opencores.org/ocsvn/vhdl_cpu_emulator/vhdl_cpu_emulator/trunk
[/] [vhdl_cpu_emulator/] [trunk/] [design_top_tb.vhd] - Diff between revs 2 and 3
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library ieee;
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library generics;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use generics.components.all;
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use work.design_top_constants.all;
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entity design_top_tb is
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port(
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clk : out std_logic_vector(1 downto 0);
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rstN : out std_logic_vector(1 downto 0);
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cpu_cs1 : out std_logic_vector(1 downto 0);
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cpu_cs2 : out std_logic_vector(1 downto 0);
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cpu_cs3 : out std_logic_vector(1 downto 0);
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cpu_we : out std_logic_vector(1 downto 0);
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cpu_a : out std_logic_vector(9 downto 0);
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cpu_d : inout std_logic_vector(15 downto 0);
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cpu_irq4 : in std_logic_vector(1 downto 0);
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cpu_irq7 : in std_logic_vector(1 downto 0)
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);
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end design_top_tb;
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architecture behavior of design_top_tb is
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component cpu_sim is
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port(
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fname : in filename;
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clk : out std_logic;
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rstN : out std_logic;
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cpu_cs1 : out std_logic;
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cpu_cs2 : out std_logic;
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cpu_cs3 : out std_logic;
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cpu_we : out std_logic;
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cpu_a : out std_logic_vector(4 downto 0);
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cpu_d : inout std_logic_vector(7 downto 0);
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cpu_irq4 : in std_logic;
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cpu_irq7 : in std_logic
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);
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end component;
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signal fnames : array2xfilename := (mk_filename("cpu1.txt"), mk_filename("cpu0.txt"));
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begin
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gen_blocks : for i in 0 to 1 generate
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cpu_sim_inst : cpu_sim port map(
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fname => fnames(i),
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clk => clk(i),
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rstN => rstN(i),
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cpu_cs1 => cpu_cs1(i),
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cpu_cs2 => cpu_cs2(i),
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cpu_cs3 => cpu_cs3(i),
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cpu_we => cpu_we(i),
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cpu_a => cpu_a(i * 5 + 4 downto i * 5),
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cpu_d => cpu_d(i * 8 + 7 downto i * 8),
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cpu_irq4 => cpu_irq4(i),
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cpu_irq7 => cpu_irq7(i)
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);
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end generate gen_blocks;
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end;
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