URL https://opencores.org/ocsvn/vhdl_cpu_emulator/vhdl_cpu_emulator/trunk

Subversion Repositories vhdl_cpu_emulator

[/] [vhdl_cpu_emulator/] [trunk/] [thr_rx_uart0.txt] - Diff between revs 2 and 3

Rev 2	Rev 3
?rev1line?	?rev2line?
	`#wait for interrupt thread to do initialization`
	`PARAMETERS STRING outfile`
	`WAIT 30 ns`
	`CLEAR outfile`

	`WHILE`

	`WAIT 3 us`

	`#check if data received interrupt`
	`vector8 tmp = int0shadow`
	`tmp &= 00000010`
	`IF tmp == 00000010`
	`int0shadow &= 11111101`
	`READ 00010111 tmp`
	`PRINT outfile tmp`
	`IF_END`

	`WHILE_END`