URL https://opencores.org/ocsvn/vhdl_cpu_emulator/vhdl_cpu_emulator/trunk

Subversion Repositories vhdl_cpu_emulator

[/] [vhdl_cpu_emulator/] [trunk/] [thr_tx_uart1.txt] - Diff between revs 2 and 3

Rev 2	Rev 3
?rev1line?	?rev2line?
	`#wait for interrupt thread to do initialization`
	`PARAMETERS vector8 txstart`
	`WAIT 30 ns`
	`#counter is now set by parameter at thread creation`

	`WHILE`

	`WAIT 3 us`

	`#check if transmit ready interrupt - from interrupt thread`
	`vector8 tmp = int1shadow`
	`tmp &= 00000001`
	`IF tmp == 00000001`
	`int1shadow &= 11111110`
	`WRITE 00011110 txstart`
	`#increment counter for transmit`
	`txstart += 00000001`
	`IF_END`

	`WHILE_END`