| Line 61... |
Line 61... |
use work.wishbone_bfm_pkg.all;
|
use work.wishbone_bfm_pkg.all;
|
|
|
-- entity ------------------------------------------------------------
|
-- entity ------------------------------------------------------------
|
entity stimulator is
|
entity stimulator is
|
generic(
|
generic(
|
g_number_of_signals : natural := 1
|
number_of_signals_g : natural := 1
|
);
|
);
|
port(
|
port(
|
wb_i : in wishbone_slave_in_t;
|
wb_i : in wishbone_slave_in_t;
|
wb_o : out wishbone_slave_out_t;
|
wb_o : out wishbone_slave_out_t;
|
|
|
signals_o : out std_logic_vector(g_number_of_signals-1 downto 0)
|
signals_o : out std_logic_vector(number_of_signals_g-1 downto 0)
|
);
|
);
|
end stimulator;
|
end stimulator;
|
|
|
--=architecture===============================================================
|
--=architecture===============================================================
|
architecture rtl of stimulator is
|
architecture rtl of stimulator is
|
--============================================================================
|
--============================================================================
|
-- signal declaration
|
-- signal declaration
|
--============================================================================
|
--============================================================================
|
signal s_register0 : std_logic_vector(wb_i.dat'left downto 0);
|
signal register0_s : std_logic_vector(wb_i.dat'left downto 0);
|
signal s_register1 : std_logic_vector(wb_i.dat'left downto 0);
|
signal register1_s : std_logic_vector(wb_i.dat'left downto 0);
|
--============================================================================
|
--============================================================================
|
begin
|
begin
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
wb_o.ack <= '1';
|
wb_o.ack <= '1';
|
wb_o.err <= '0';
|
wb_o.err <= '0';
|
| Line 91... |
Line 91... |
-- read data multiplexer
|
-- read data multiplexer
|
proc_read_data_mux : process (all)
|
proc_read_data_mux : process (all)
|
begin
|
begin
|
case wb_i.adr(27 downto 0) is
|
case wb_i.adr(27 downto 0) is
|
when 28X"000_0000" =>
|
when 28X"000_0000" =>
|
wb_o.dat <= s_register0;
|
wb_o.dat <= register0_s;
|
when 28X"000_0004" =>
|
when 28X"000_0004" =>
|
wb_o.dat <= s_register1;
|
wb_o.dat <= register1_s;
|
when others =>
|
when others =>
|
wb_o.dat <= (others =>'U');
|
wb_o.dat <= (others =>'U');
|
end case;
|
end case;
|
end process;
|
end process;
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
proc_avalon_write_data : process (all)
|
proc_avalon_write_data : process (all)
|
begin
|
begin
|
if (wb_i.rst = '1') then
|
if (wb_i.rst = '1') then
|
s_register0 <= (others => '0');
|
register0_s <= (others => '0');
|
s_register1 <= (others => '0');
|
register1_s <= (others => '0');
|
elsif (rising_edge(wb_i.clk)) then
|
elsif (rising_edge(wb_i.clk)) then
|
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
|
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
|
case wb_i.adr(27 downto 0) is
|
case wb_i.adr(27 downto 0) is
|
when 28X"000_0000" =>
|
when 28X"000_0000" =>
|
s_register0 <= wb_i.dat;
|
register0_s <= wb_i.dat;
|
when 28X"000_0004" =>
|
when 28X"000_0004" =>
|
s_register1 <= wb_i.dat;
|
register1_s <= wb_i.dat;
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
signals_o <= s_register0(signals_o'left downto 0);
|
signals_o <= register0_s(signals_o'left downto 0);
|
--============================================================================
|
--============================================================================
|
end rtl; --stimulator
|
end rtl; --stimulator
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- end of file ----
|
---- end of file ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
No newline at end of file
|
No newline at end of file
|
