| Line 75... |
Line 75... |
end entity tb_top;
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end entity tb_top;
|
|
|
-- architecture ------------------------------------------------------
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-- architecture ------------------------------------------------------
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architecture rtl of tb_top is
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architecture rtl of tb_top is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz
|
constant wb_clock_period_g : time := 20.0 ns; -- 50 mhz
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top
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signal wb_bfm_out_s : wishbone_bfm_master_out_t; -- from testcase_top
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signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top
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signal wb_bfm_in_s : wishbone_bfm_master_in_t; -- to testcase_top
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|
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signal s_wb_master_out : wishbone_master_out_t; -- from wb_decoder
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signal wb_master_out_s : wishbone_master_out_t; -- from wb_decoder
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signal s_wb_master_in : wishbone_master_in_t; -- to wb_decoder
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signal wb_master_in_s : wishbone_master_in_t; -- to wb_decoder
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|
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constant number_of_wb_slaves_c : integer := 2;
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constant number_of_wb_slaves_c : integer := 2;
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signal s_wb_slaves_in : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0);
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signal wb_slaves_in_s : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0);
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signal s_wb_slaves_out : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0);
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signal wb_slaves_out_s : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0);
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|
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signal s_wb_clock : std_logic := '0';
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signal wb_clock_s : std_logic := '0';
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signal s_wb_clock_locked : std_logic := '0';
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signal wb_clock_locked_s : std_logic := '0';
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signal s_wb_reset_p1 : std_logic := '1';
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signal wb_reset_p1_s : std_logic := '1';
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signal s_wb_reset_p2 : std_logic := '1';
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signal wb_reset_p2_s : std_logic := '1';
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signal s_wb_reset : std_logic := '1';
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signal wb_reset_s : std_logic := '1';
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|
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constant number_of_stimulus_signals_c : integer := 8;
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constant number_of_stimulus_signals_c : integer := 8;
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constant number_of_verify_signals_c : integer := 8;
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constant number_of_verify_signals_c : integer := 8;
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signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
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signal stimulus_s : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
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signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
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signal verify_s : std_logic_vector(number_of_verify_signals_c-1 downto 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
begin
|
begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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--clocks---------------------------------------------------------------------
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--clocks---------------------------------------------------------------------
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wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
|
wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
|
begin
|
begin
|
s_wb_clock <= '0';
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wb_clock_s <= '0';
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wait for g_wb_clock_period/2;
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wait for wb_clock_period_g/2;
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s_wb_clock <= '1';
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wb_clock_s <= '1';
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wait for g_wb_clock_period/2;
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wait for wb_clock_period_g/2;
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s_wb_clock_locked <= '1';
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wb_clock_locked_s <= '1';
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end process;
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end process;
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
synchronize_reset_proc : process(all)
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synchronize_reset_proc : process(all)
|
begin
|
begin
|
if (s_wb_clock_locked = '0') then
|
if (wb_clock_locked_s = '0') then
|
s_wb_reset_p1 <= '1';
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wb_reset_p1_s <= '1';
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s_wb_reset_p2 <= '1';
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wb_reset_p2_s <= '1';
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elsif (rising_edge(s_wb_clock)) then
|
elsif (rising_edge(wb_clock_s)) then
|
s_wb_reset_p1 <= '0'; -- or s_tc_reset;
|
wb_reset_p1_s <= '0'; -- or tc_reset_s;
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s_wb_reset_p2 <= s_wb_reset_p1;
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wb_reset_p2_s <= wb_reset_p1_s;
|
end if;
|
end if;
|
end process;
|
end process;
|
s_wb_reset <= s_wb_reset_p2;
|
wb_reset_s <= wb_reset_p2_s;
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- instance of test case "player"; runs tc_xxxx modules
|
-- instance of test case "player"; runs tc_xxxx modules
|
tc_top_inst : entity work.tc_top
|
tc_top_inst : entity work.tc_top
|
port map (
|
port map (
|
wb_o => s_wb_bfm_out,
|
wb_o => wb_bfm_out_s,
|
wb_i => s_wb_bfm_in
|
wb_i => wb_bfm_in_s
|
);
|
);
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- splits the test case wb bus for all stimulation and verifier modules.
|
-- splits the test case wb bus for all stimulation and verifier modules.
|
-- decodes the given bits (g_decoded_address_msb:g_decoded_address_lsb) and#
|
-- decodes the given bits (decoded_address_msb_g:decoded_address_lsb_g) and#
|
-- compares them to 0..n, with n=(g_number_of_ports-1)
|
-- compares them to 0..n, with n=(number_of_ports_g-1)
|
proc_readdata_decoder : process (all)
|
proc_readdata_decoder : process (all)
|
begin
|
begin
|
s_wb_bfm_in.dat <= (others => 'U');
|
wb_bfm_in_s.dat <= (others => 'U');
|
s_wb_bfm_in.ack <= '1';
|
wb_bfm_in_s.ack <= '1';
|
s_wb_bfm_in.clk <= s_wb_clock;
|
wb_bfm_in_s.clk <= wb_clock_s;
|
s_wb_bfm_in.int <= '0';
|
wb_bfm_in_s.int <= '0';
|
s_wb_bfm_in.rst <= s_wb_reset;
|
wb_bfm_in_s.rst <= wb_reset_s;
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for I in number_of_wb_slaves_c-1 downto 0 loop
|
for I in number_of_wb_slaves_c-1 downto 0 loop
|
s_wb_slaves_in(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
|
wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
|
s_wb_slaves_in(I).clk <= s_wb_clock;
|
wb_slaves_in_s(I).clk <= wb_clock_s;
|
s_wb_slaves_in(I).rst <= s_wb_reset OR s_wb_bfm_out.rst;
|
wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst;
|
if ( s_wb_bfm_out.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
|
if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
|
s_wb_bfm_in.dat <= s_wb_slaves_out(I).dat;
|
wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat;
|
s_wb_bfm_in.ack <= s_wb_slaves_out(I).ack;
|
wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack;
|
s_wb_slaves_in(I).dat <= s_wb_bfm_out.dat;
|
wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat;
|
s_wb_slaves_in(I).tgd <= s_wb_bfm_out.tgd;
|
wb_slaves_in_s(I).tgd <= wb_bfm_out_s.tgd;
|
s_wb_slaves_in(I).adr <= s_wb_bfm_out.adr;
|
wb_slaves_in_s(I).adr <= wb_bfm_out_s.adr;
|
s_wb_slaves_in(I).cyc <= s_wb_bfm_out.cyc;
|
wb_slaves_in_s(I).cyc <= wb_bfm_out_s.cyc;
|
s_wb_slaves_in(I).lock <= s_wb_bfm_out.lock;
|
wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock;
|
s_wb_slaves_in(I).sel <= s_wb_bfm_out.sel;
|
wb_slaves_in_s(I).sel <= wb_bfm_out_s.sel;
|
s_wb_slaves_in(I).stb <= s_wb_bfm_out.stb;
|
wb_slaves_in_s(I).stb <= wb_bfm_out_s.stb;
|
s_wb_slaves_in(I).tga <= s_wb_bfm_out.tga;
|
wb_slaves_in_s(I).tga <= wb_bfm_out_s.tga;
|
s_wb_slaves_in(I).tgc <= s_wb_bfm_out.tgc;
|
wb_slaves_in_s(I).tgc <= wb_bfm_out_s.tgc;
|
s_wb_slaves_in(I).we <= s_wb_bfm_out.we;
|
wb_slaves_in_s(I).we <= wb_bfm_out_s.we;
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end process;
|
end process;
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- instance of design under test
|
-- instance of design under test
|
core_top_inst : entity work.core_top
|
core_top_inst : entity work.core_top
|
generic map(
|
generic map(
|
g_number_of_in_signals => number_of_stimulus_signals_c,
|
number_of_in_signals_g => number_of_stimulus_signals_c,
|
g_number_of_out_signals => number_of_verify_signals_c
|
number_of_out_signals_g => number_of_verify_signals_c
|
)
|
)
|
port map(
|
port map(
|
clock_i => s_wb_clock,
|
clock_i => wb_clock_s,
|
reset_i => s_wb_reset,
|
reset_i => wb_reset_s,
|
signals_i => s_stimulus,
|
signals_i => stimulus_s,
|
signals_o => s_verify
|
signals_o => verify_s
|
);
|
);
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- instance of stimulator
|
-- instance of stimulator
|
stimulator_inst : entity work.stimulator
|
stimulator_inst : entity work.stimulator
|
generic map(
|
generic map(
|
g_number_of_signals => number_of_stimulus_signals_c
|
number_of_signals_g => number_of_stimulus_signals_c
|
)
|
)
|
port map(
|
port map(
|
wb_i => s_wb_slaves_in(0),
|
wb_i => wb_slaves_in_s(0),
|
wb_o => s_wb_slaves_out(0),
|
wb_o => wb_slaves_out_s(0),
|
signals_o => s_stimulus
|
signals_o => stimulus_s
|
);
|
);
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- instance of stimulator
|
-- instance of stimulator
|
verifier_inst : entity work.verifier
|
verifier_inst : entity work.verifier
|
generic map(
|
generic map(
|
g_number_of_signals => number_of_verify_signals_c
|
number_of_signals_g => number_of_verify_signals_c
|
)
|
)
|
port map(
|
port map(
|
wb_i => s_wb_slaves_in(1),
|
wb_i => wb_slaves_in_s(1),
|
wb_o => s_wb_slaves_out(1),
|
wb_o => wb_slaves_out_s(1),
|
signals_i => s_verify
|
signals_i => verify_s
|
);
|
);
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
end rtl;
|
end rtl;
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- end of file ----
|
---- end of file ----
|
