| Line 63... |
Line 63... |
use work.wishbone_bfm_pkg.all;
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use work.wishbone_bfm_pkg.all;
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|
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-- entity ------------------------------------------------------------
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-- entity ------------------------------------------------------------
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entity verifier is
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entity verifier is
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generic(
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generic(
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g_number_of_signals : natural := 1
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number_of_signals_g : natural := 1
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);
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);
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port(
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port(
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wb_i : in wishbone_slave_in_t;
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wb_i : in wishbone_slave_in_t;
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wb_o : out wishbone_slave_out_t;
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wb_o : out wishbone_slave_out_t;
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|
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signals_i : in std_logic_vector(g_number_of_signals-1 downto 0)
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signals_i : in std_logic_vector(number_of_signals_g-1 downto 0)
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);
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);
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end verifier;
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end verifier;
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|
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-- architecture ----------------------------------------------------------------
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-- architecture ----------------------------------------------------------------
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architecture rtl of verifier is
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architecture rtl of verifier is
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- signal declaration
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-- signal declaration
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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signal s_register0 : std_logic_vector(31 downto 0);
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signal register0_s : std_logic_vector(31 downto 0);
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signal s_register1 : std_logic_vector(31 downto 0);
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signal register1_s : std_logic_vector(31 downto 0);
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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begin
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begin
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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wb_o.ack <= '1';
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wb_o.ack <= '1';
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wb_o.err <= '0';
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wb_o.err <= '0';
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| Line 94... |
Line 94... |
-- read data multiplexer
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-- read data multiplexer
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proc_read_data_mux : process (all)
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proc_read_data_mux : process (all)
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begin
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begin
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case wb_i.adr(27 downto 0) is
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case wb_i.adr(27 downto 0) is
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when 28X"000_0000" =>
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when 28X"000_0000" =>
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wb_o.dat <= s_register0;
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wb_o.dat <= register0_s;
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when 28X"000_0004" =>
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when 28X"000_0004" =>
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wb_o.dat <= s_register1;
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wb_o.dat <= register1_s;
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when 28X"000_0008" =>
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when 28X"000_0008" =>
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wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
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wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
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when others =>
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when others =>
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wb_o.dat <= (others =>'U');
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wb_o.dat <= (others =>'U');
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end case;
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end case;
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| Line 108... |
Line 108... |
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- write signals to control the verifier
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-- write signals to control the verifier
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proc_avalon_write_data : process (all)
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proc_avalon_write_data : process (all)
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begin
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begin
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if (wb_i.rst = '1') then
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if (wb_i.rst = '1') then
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s_register0 <= (others => '0');
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register0_s <= (others => '0');
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s_register1 <= (others => '0');
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register1_s <= (others => '0');
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elsif (rising_edge(wb_i.clk)) then
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elsif (rising_edge(wb_i.clk)) then
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if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
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if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
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case wb_i.adr(27 downto 0) is
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case wb_i.adr(27 downto 0) is
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when 28X"000_0000" =>
|
when 28X"000_0000" =>
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s_register0 <= wb_i.dat;
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register0_s <= wb_i.dat;
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when 28X"000_0004" =>
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when 28X"000_0004" =>
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s_register1 <= wb_i.dat;
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register1_s <= wb_i.dat;
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when others =>
|
when others =>
|
end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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