| Line 19... |
Line 19... |
---- ----
|
---- ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- SVN information
|
---- SVN information
|
----
|
----
|
---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/verifier.vhd $
|
---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/verifier.vhd $
|
---- $Revision: 14 $
|
---- $Revision: 15 $
|
---- $Date: 2018-07-22 16:27:41 +0200 (Sun, 22 Jul 2018) $
|
---- $Date: 2018-07-22 17:14:42 +0200 (Sun, 22 Jul 2018) $
|
---- $Author: sinx $
|
---- $Author: sinx $
|
---- $Id: verifier.vhd 14 2018-07-22 14:27:41Z sinx $
|
---- $Id: verifier.vhd 15 2018-07-22 15:14:42Z sinx $
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
| Line 105... |
Line 105... |
wb_o.dat <= (others =>'U');
|
wb_o.dat <= (others =>'U');
|
end case;
|
end case;
|
end process;
|
end process;
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- write signals to control the verifier
|
-- write signals to control the verifier
|
proc_avalon_write_data : process (all)
|
proc_wb_write_data : process (all)
|
begin
|
begin
|
if (wb_i.rst = '1') then
|
if (wb_i.rst = '1') then
|
register0_s <= (others => '0');
|
register0_s <= (others => '0');
|
register1_s <= (others => '0');
|
register1_s <= (others => '0');
|
elsif (rising_edge(wb_i.clk)) then
|
elsif (rising_edge(wb_i.clk)) then
|
