URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [top.vhd] - Diff between revs 4 and 5

Rev 4	Rev 5
Line 71...	Line 71...

`-- architecture ------------------------------------------------------`	`-- architecture ------------------------------------------------------`
`architecture rtl of top is`	`architecture rtl of top is`
`-----------------------------------------------------------------------------`	`-----------------------------------------------------------------------------`
`-- constant number_of_stimulus_signals_c : integer := 8;`	`-- constant number_of_stimulus_signals_c : integer := 8;`
`-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);`	`-- signal verify_s : std_logic_vector(number_of_verify_signals_c-1 downto 0);`
`-----------------------------------------------------------------------------`	`-----------------------------------------------------------------------------`
`begin`	`begin`
`-----------------------------------------------------------------------------`	`-----------------------------------------------------------------------------`
`-- instance of design`	`-- instance of design`
`core_top_inst : entity work.core_top`	`core_top_inst : entity work.core_top`
`generic map(`	`generic map(`
`g_number_of_in_signals => 8,`	`number_of_in_signals_g => 8,`
`g_number_of_out_signals => 8`	`number_of_out_signals_g => 8`
`)`	`)`
`port map(`	`port map(`
`clock_i => clock_i,`	`clock_i => clock_i,`
`reset_i => '0',`	`reset_i => '0',`
`signals_i => signals_i,`	`signals_i => signals_i,`