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--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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signal s_axis_input_tready_int : std_logic;
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signal s_axis_input_tready_int : std_logic;
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begin
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begin
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-- We are ready, when we are allowed to write to the output, or the output is idle.
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-- We are ready, when we are allowed to write to the output, or the output is idle.
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-- s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
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s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' else
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s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' else
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'0';
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'0';
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-- Connect internal versions of signal to output port.
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-- Connect internal versions of signal to output port.
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s_axis_input_tready <= s_axis_input_tready_int;
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s_axis_input_tready <= s_axis_input_tready_int;
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if rst = '1' then
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if rst = '1' then
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m_axis_output_tvalid_int <= '0';
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m_axis_output_tvalid_int <= '0';
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m_axis_output_tdata <= (others => '0');
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m_axis_output_tdata <= (others => '0');
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m_axis_output_tlast <= '0';
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m_axis_output_tlast <= '0';
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else
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else
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if m_axis_output_tvalid_int = '1' and m_axis_output_tready = '1' then
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m_axis_output_tvalid_int <= '0';
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m_axis_output_tlast <= '0';
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end if;
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if s_axis_input_tready_int = '1' and s_axis_input_tvalid = '1' then
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if s_axis_input_tready_int = '1' and s_axis_input_tvalid = '1' then
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v_branch_result := 0;
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v_branch_result := 0;
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for i in NUMBER_PARITY_BITS - 1 downto 0 loop
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for i in NUMBER_PARITY_BITS - 1 downto 0 loop
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--
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--
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-- Either the value is added or subtrcated, depending on
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-- Either the value is added or subtracted, depending on
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-- the current branch metric we are computing.
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-- the current branch metric we are computing.
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--
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--
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if EDGE_WEIGHT(i) = '0' then
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if EDGE_WEIGHT(i) = '0' then
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v_branch_result := v_branch_result + to_integer(s_axis_input_tdata(i));
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v_branch_result := v_branch_result + to_integer(s_axis_input_tdata(i));
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else
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else
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v_branch_result := v_branch_result - to_integer(s_axis_input_tdata(i));
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v_branch_result := v_branch_result - to_integer(s_axis_input_tdata(i));
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end if;
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end if;
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end loop;
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end loop;
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m_axis_output_tdata <= std_logic_vector(to_signed(v_branch_result, BW_BRANCH_RESULT));
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m_axis_output_tdata <= std_logic_vector(to_signed(v_branch_result, BW_BRANCH_RESULT));
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m_axis_output_tvalid_int <= '1';
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m_axis_output_tlast <= s_axis_input_tlast;
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end if;
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end if;
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m_axis_output_tvalid_int <= s_axis_input_tvalid;
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m_axis_output_tlast <= s_axis_input_tlast;
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end if;
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end if;
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end if;
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end if;
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end process pr_branch;
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end process pr_branch;
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end architecture rtl;
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end architecture rtl;
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