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# $Id: w11a_tb_guide.txt 352 2011-01-02 13:01:37Z mueller $
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# $Id: w11a_tb_guide.txt 376 2011-04-17 12:24:07Z mueller $
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Guide to running w11a test benches
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Guide to running w11a test benches
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Table of content:
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Table of content:
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-> 1220255.0 ns 61003: DONE
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-> 1220255.0 ns 61003: DONE
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-> real 1m9.738s user 1m9.588s sys 0m0.096s
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-> real 1m9.738s user 1m9.588s sys 0m0.096s
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3. System tests benches ---------------------------------------------------
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3. System tests benches ---------------------------------------------------
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The system tests allow to verify to verify the full 11/70 SoC design.
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The system tests allow to verify to verify a full system design.
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In this case vhdl test bench code contains
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In this case vhdl test bench code contains
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- (simple) models of the memories used on the FPGA boards
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- (simple) models of the memories used on the FPGA boards
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- drivers for the rlink connection (currently just serialport)
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- drivers for the rlink connection (currently just serialport)
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- code to interface the rlink data stream to a UNIX 'named pipe',
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- code to interface the rlink data stream to a UNIX 'named pipe',
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implemented with a C routine which is called via VHPI from VHDL.
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implemented with a C routine which is called via VHPI from VHDL.
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This way the whole ghdl simulation can be controlled via a di-directional
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This way the whole ghdl simulation can be controlled via a di-directional
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byte stream.
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byte stream.
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The rlink backend process, currently a perl script named pi_rri, can connect
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The rlink backend process can connect either via a named pipe to a ghdl
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either via a named pipe to a ghdl simulation, or via a serial port to a
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simulation, or via a serial port to a FPGA board. This way the same tests
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FPGA board. This way the same tests can be executed in simulation and
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can be executed in simulation and on real hardware.
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on real hardware.
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Currently two backend implementations are available:
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- pi_rri: written in perl (old, slow, but full functionality)
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- ti_tti: written in C++ and Tcl (new, fast, but as of V0.53 only with
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limited functionality; will replace pi_rri).
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4. Available system tests benches -----------------------------------------
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4. Available system tests benches -----------------------------------------
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4a. rlink tester -----------------------------------------------------
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The sys_tst_rlink design is a test target for validating the rlink
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and rbus functionality at all levels.
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- sys_tst_rlink_n2 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
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make tb_tst_rlink_n2
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time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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tee tb_tst_rlink_n2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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-> 1769140.0 ns 88446: DONE
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-> real 0m15.289s
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4b. w11a systems -----------------------------------------------------
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The stimulus file used in the w11a core test can be executed in the
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The stimulus file used in the w11a core test can be executed in the
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full system context (both s3board and nexys2 versions) with the
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full system context (both s3board and nexys2 versions) with the
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following commands. Note that the cycle number printed in the DONE
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following commands. Note that the cycle number printed in the DONE
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line can now vary slightly because the response time of the rlink
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line can now vary slightly because the response time of the rlink
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backend process and thus scheduling of backend vs. ghdl process
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backend process and thus scheduling of backend vs. ghdl process
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can affect the result.
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can affect the result.
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- sys_w11a_s3 system test
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- sys_w11a_s3 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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make tb_w11a_s3
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make tb_w11a_s3
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time pi_rri --fifo --timeout=40. --cmax=3 \
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time pi_rri --fifo --timeout=40. --cmax=3 \
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--run="tbw tb_w11a_s3" -- \
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--run="tbw tb_w11a_s3" -- \
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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-> 7757655.0 ns 387873: DONE
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-> 7757655.0 ns 387873: DONE
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-> real 0m49.835s user 0m50.203s sys 0m0.696s
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-> real 0m49.835s user 0m50.203s sys 0m0.696s
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- sys_w11a_n2 system test
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- sys_w11a_n2 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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make tb_w11a_n2
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make tb_w11a_n2
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time pi_rri --fifo --timeout=40. --cmax=3 \
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time pi_rri --fifo --timeout=40. --cmax=3 \
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--run="tbw tb_w11a_n2" -- \
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--run="tbw tb_w11a_n2" -- \
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