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# $Id: w11a_tb_guide.txt 433 2011-11-27 22:04:39Z mueller $
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# $Id: w11a_tb_guide.txt 442 2011-12-23 10:03:28Z mueller $
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Guide to running w11a test benches
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Guide to running w11a test benches
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Table of content:
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Table of content:
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time tbw tb_pdp11core_ssim |\
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time tbw tb_pdp11core_ssim |\
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tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
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tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
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-> 1220255.0 ns 61003: DONE
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-> 1220255.0 ns 61003: DONE
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-> real 1m09.738s user 1m09.588s sys 0m00.096s
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-> real 1m09.738s user 1m09.588s sys 0m00.096s
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- s3board sram controller test
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cd $RETROBASE/rtl/bplib/s3board/tb
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make tb_s3_sram_memctl
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time tbw tb_s3_sram_memctl |\
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tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
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-> 5015.0 ns 241: DONE
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-> real 0m00.113s user 0m00.068s sys 0m00.016s
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- nexys2/nexys3 cram controller test
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cd $RETROBASE/rtl/bplib/nxcramlib/tb
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make tb_nx_cram_memctl_as
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time tbw tb_nx_cram_memctl_as |\
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tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
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-> 24272.5 ns 1204: DONE
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-> real 0m00.343s user 0m00.248s sys 0m00.100s
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3. System tests benches ---------------------------------------------------
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3. System tests benches ---------------------------------------------------
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The system tests allow to verify to verify a full system design.
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The system tests allow to verify to verify a full system design.
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In this case vhdl test bench code contains
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In this case vhdl test bench code contains
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- (simple) models of the memories used on the FPGA boards
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- (simple) models of the memories used on the FPGA boards
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simulation, or via a serial port to a FPGA board. This way the same tests
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simulation, or via a serial port to a FPGA board. This way the same tests
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can be executed in simulation and on real hardware.
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can be executed in simulation and on real hardware.
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Currently two backend implementations are available:
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Currently two backend implementations are available:
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- pi_rri: written in perl (old, slow, but full functionality)
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- pi_rri: written in perl (old, slow, but full functionality)
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- ti_tti: written in C++ and Tcl (new, fast, but as of V0.53 only with
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- ti_tti: written in C++ and Tcl (new, fast, but as of V0.55 only with
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limited functionality; will replace pi_rri).
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limited functionality; will replace pi_rri).
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4. Available system tests benches -----------------------------------------
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4. Available system tests benches -----------------------------------------
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4a. rlink tester -----------------------------------------------------
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4a. serport tester -- --------------------------------------------
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The sys_tst_serloop design is a test target for validating the serial
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link UART stack. Send and receive throughput as well as loop-back tests
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are supported
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- sys_tst_serloop_s3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
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make tb_tst_serloop_s3
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time tbw tb_tst_serloop_s3 |\
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tee tb_tst_serloop_s3_dsim.log | egrep "(FAIL|DONE)"
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-> 301353.3 ns 18068: DONE
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-> real 0m1.422s user 0m1.372s sys 0m0.024s
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- sys_tst_serloop_n2 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
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make tb_tst_serloop1_n2
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time tbw tb_tst_serloop1_n2 |\
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tee tb_tst_serloop1_n2_dsim.log | egrep "(FAIL|DONE)"
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-> 361560.0 ns 18068: DONE
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-> real 0m1.341s user 0m1.340s sys 0m0.016s
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make tb_tst_serloop2_n2
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time tbw tb_tst_serloop2_n2 |\
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tee tb_tst_serloop2_n2_dsim.log | egrep "(FAIL|DONE)"
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-> 304353.3 ns 18248: DONE
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-> real 0m1.933s user 0m1.924s sys 0m0.024s
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- sys_tst_serloop_n3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
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make tb_tst_serloop1_n3
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time tbw tb_tst_serloop1_n3 |\
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tee tb_tst_serloop1_n3_dsim.log | egrep "(FAIL|DONE)"
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-> 361560.0 ns 18068: DONE
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-> real 0m1.371s user 0m1.372s sys 0m0.016s
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4b. rlink tester -----------------------------------------------------
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The sys_tst_rlink design is a test target for validating the rlink
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The sys_tst_rlink design is a test target for validating the rlink
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and rbus functionality at all levels.
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and rbus functionality at all levels.
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- sys_tst_rlink_s3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
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make tb_tst_rlink_s3
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time ti_rri --run="tbw tb_tst_rlink_s3" --fifo --logl=3 -- \
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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tee tb_tst_rlink_s3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 1822195.0 ns 91100: DONE
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-> real 0m13.281s
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- sys_tst_rlink_n2 test bench
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- sys_tst_rlink_n2 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
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make tb_tst_rlink_n2
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make tb_tst_rlink_n2
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time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
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time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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tee tb_tst_rlink_n2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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tee tb_tst_rlink_n2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 1769140.0 ns 88446: DONE
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-> 1769140.0 ns 88446: DONE
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-> real 0m15.289s
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-> real 0m15.289s
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- sys_tst_rlink_n3 test bench
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- sys_tst_rlink_n3 test bench
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
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make tb_tst_rlink_n3
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make tb_tst_rlink_n3
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time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \
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time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
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tee tb_tst_rlink_n3_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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tee tb_tst_rlink_n3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 893590.0 ns 89338: DONE
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-> 893590.0 ns 89338: DONE
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-> real 0m9.510s
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-> real 0m9.510s
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4b. w11a systems -----------------------------------------------------
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4c. w11a systems -----------------------------------------------------
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The stimulus file used in the w11a core test can be executed in the
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The stimulus file used in the w11a core test can be executed in the
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full system context (both s3board and nexys2 versions) with the
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full system context (both s3board and nexys2 versions) with the
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following commands. Note that the cycle number printed in the DONE
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following commands. Note that the cycle number printed in the DONE
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line can now vary slightly because the response time of the rlink
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line can now vary slightly because the response time of the rlink
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
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make tb_w11a_s3
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make tb_w11a_s3
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time pi_rri --fifo --timeout=40. --cmax=3 \
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time pi_rri --fifo --timeout=40. --cmax=3 \
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--run="tbw tb_w11a_s3" -- \
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--run="tbw tb_w11a_s3" -- \
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 7757655.0 ns 387873: DONE
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-> 7852095.0 ns 392595: DONE
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-> real 0m49.835s user 0m50.203s sys 0m00.696s
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-> real 0m49.835s user 0m50.203s sys 0m00.696s
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- sys_w11a_n2 test bench
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- sys_w11a_n2 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
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make tb_w11a_n2
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make tb_w11a_n2
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time pi_rri --fifo --timeout=40. --cmax=3 \
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time pi_rri --fifo --timeout=40. --cmax=3 \
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--run="tbw tb_w11a_n2" -- \
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--run="tbw tb_w11a_n2" -- \
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 6673237.2 ns 387035: DONE
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-> 7836580.0 ns 391818: DONE
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-> real 0m56.173s user 0m56.612s sys 0m00.604s
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-> real 1m0.854s user 1m1.332s sys 0m0.800s
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- sys_w11a_n3 test bench
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- sys_w11a_n3 test bench
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
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make tb_w11a_n3
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make tb_w11a_n3
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time pi_rri --fifo --timeout=40. --cmax=3 \
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time pi_rri --fifo --timeout=40. --cmax=3 \
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--run="tbw tb_w11a_n3" -- \
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--run="tbw tb_w11a_n3" -- \
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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@../../../../w11a/tb/tb_pdp11core_stim.dat |\
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tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
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tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
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-> 4593598.2 ns 390438: DONE
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-> 3956540.0 ns 395633: DONE
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-> real 0m55.326s user 0m55.711s sys 0m00.752s
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-> real 1m13.811s user 1m14.389s sys 0m0.948s
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