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-- $Id: fx2_2fifoctl_ic.vhd 453 2012-01-15 17:51:18Z mueller $
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-- $Id: fx2_2fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $
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--
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--
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-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 13.3; ghdl 0.29
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-- Tool versions: xst 13.3; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101 173 64 159 s 8.3/7.4
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-- 2013-01-04 469 13.3 O76x xc3s1200e-4 112 172 64 169 s 7.4/7.4
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-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101? 173 64 159 s 8.3/7.4
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-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5
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-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2013-01-04 469 1.2 BUGFIX: redo rx logic, now properly pipelined
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-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows
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-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows
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-- 2012-01-09 451 1.0 Initial version
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-- 2012-01-09 451 1.0 Initial version
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-- 2012-01-01 448 0.5 First draft
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-- 2012-01-01 448 0.5 First draft
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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s_idle, -- s_idle: idle state
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s_idle, -- s_idle: idle state
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s_rxprep0, -- s_rxprep0: switch to rx-fifo
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s_rxprep0, -- s_rxprep0: switch to rx-fifo
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s_rxprep1, -- s_rxprep1: fifo addr setup
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s_rxprep1, -- s_rxprep1: fifo addr setup
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s_rxprep2, -- s_rxprep2: wait for flags
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s_rxprep2, -- s_rxprep2: wait for flags
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s_rxdisp, -- s_rxdisp: read, dispatch
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s_rxdisp, -- s_rxdisp: read, dispatch
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s_rxpipe, -- s_rxpipe: read, pipe drain
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s_rxpipe, -- s_rxpipe: read, pipe wait
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s_txprep0, -- s_txprep0: switch to tx-fifo
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s_txprep0, -- s_txprep0: switch to tx-fifo
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s_txprep1, -- s_txprep1: fifo addr setup
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s_txprep1, -- s_txprep1: fifo addr setup
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s_txprep2, -- s_txprep2: wait for flags
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s_txprep2, -- s_txprep2: wait for flags
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s_txdisp -- s_txdisp: write, dispatch
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s_txdisp -- s_txdisp: write, dispatch
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);
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);
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type regs_type is record
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type regs_type is record
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state : state_type; -- state
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state : state_type; -- state
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petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
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petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
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pepend : slbit; -- pktend pending
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pepend : slbit; -- pktend pending
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rxpipe : slbit; -- read transaction in flight
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rxpipe1 : slbit; -- read pipe 1: iob capture stage
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rxpipe2 : slbit; -- read pipe 2: fifo write stage
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ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
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ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
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moni_ep4_sel : slbit; -- ep4 (rx) select
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moni_ep4_sel : slbit; -- ep4 (rx) select
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moni_ep6_sel : slbit; -- ep6 (tx) select
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moni_ep6_sel : slbit; -- ep6 (tx) select
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moni_ep4_pf : slbit; -- ep4 (rx) prog flag
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moni_ep4_pf : slbit; -- ep4 (rx) prog flag
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moni_ep6_pf : slbit; -- ep6 (tx) prog flag
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moni_ep6_pf : slbit; -- ep6 (tx) prog flag
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constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
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constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle, -- state
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s_idle, -- state
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petocnt_init, -- petocnt
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petocnt_init, -- petocnt
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'0','0', -- pepend,rxpipe
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'0', -- pepend
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'0','0', -- rxpipe1, rxpipe2
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ccnt_init, -- ccnt
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ccnt_init, -- ccnt
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'0','0', -- moni_ep(4|6)_sel
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'0','0', -- moni_ep(4|6)_sel
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'0','0' -- moni_ep(4|6)_pf
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'0','0' -- moni_ep(4|6)_pf
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);
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);
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variable idata_cei : slbit := '0';
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variable idata_cei : slbit := '0';
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variable idata_ceo : slbit := '0';
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variable idata_ceo : slbit := '0';
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variable idata_oe : slbit := '0';
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variable idata_oe : slbit := '0';
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variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
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variable slrxok : slbit := '0';
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variable slrxok : slbit := '0';
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variable sltxok : slbit := '0';
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variable sltxok : slbit := '0';
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variable pipeok : slbit := '0';
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variable pipeok : slbit := '0';
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variable cc_clr : slbit := '0';
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variable cc_clr : slbit := '0';
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idata_cei := '0';
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idata_cei := '0';
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idata_ceo := '0';
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idata_ceo := '0';
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idata_oe := '0';
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idata_oe := '0';
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imoni := fx2ctl_moni_init;
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slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
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slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
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sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
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sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
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pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
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pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
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cc_clr := '0';
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cc_clr := '0';
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cc_done := '1';
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cc_done := '1';
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else
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else
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cc_done := '0';
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cc_done := '0';
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end if;
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end if;
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n.rxpipe1 := '0';
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case r.state is
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case r.state is
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when s_idle => -- s_idle:
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when s_idle => -- s_idle:
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if slrxok='1' and RXFIFO_BUSY='0' then
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if slrxok='1' and RXFIFO_BUSY='0' then
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ififo_ce := '1';
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ififo_ce := '1';
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ififo := c_rxfifo;
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ififo := c_rxfifo;
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isloe := '1';
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isloe := '1';
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n.state := s_rxdisp;
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n.state := s_rxdisp;
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when s_rxdisp => -- s_rxdisp: read, dispatch
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when s_rxdisp => -- s_rxdisp: read, dispatch
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isloe := '1';
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isloe := '1';
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if r.rxpipe = '1' then -- read in flight ?
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irxfifo_ena := '1'; -- capture rxdata
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n.rxpipe := '0';
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end if;
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-- if chunk done and tx or pe pending and possible
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-- if chunk done and tx or pe pending and possible
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if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
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if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
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n.state := s_txprep0;
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if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
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n.state := s_rxdisp; -- wait
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else
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n.state := s_txprep0; -- otherwise switch to tx flow
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end if;
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-- if more rx to do and possible
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-- if more rx to do and possible
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elsif slrxok='1' and RXFIFO_BUSY='0' then
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elsif slrxok='1' and unsigned(RXSIZE_FX2)>3 then -- !thres must be >3!
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cc_cnt := '1';
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idata_cei := '1';
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islrd := '1';
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islrd := '1';
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if false and pipeok='1' and unsigned(RXSIZE_FX2)>2 then
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cc_cnt := '1';
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n.rxpipe := '1';
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n.rxpipe1 := '1';
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n.state := s_rxdisp;
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if pipeok='1' then
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n.state := s_rxdisp; -- 1 cycle read
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--n.state := s_rxprep2; -- 2 cycle read
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else
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else
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n.state := s_rxpipe;
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n.state := s_rxpipe;
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end if;
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end if;
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-- otherwise back to idle
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-- otherwise back to idle
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else
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else
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n.state := s_idle;
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if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
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n.state := s_rxdisp; -- wait
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else
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n.state := s_idle; -- to idle
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end if;
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end if;
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end if;
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when s_rxpipe => -- s_rxpipe: read, pipe drain
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when s_rxpipe => -- s_rxpipe: read, pipe wait
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isloe := '1';
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isloe := '1';
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irxfifo_ena := '1'; -- capture rxdata
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if pipeok='1' and unsigned(RXSIZE_FX2)>1 then
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n.state := s_rxdisp;
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else
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n.state := s_rxprep2;
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n.state := s_rxprep2;
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end if;
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when s_txprep0 => -- s_txprep0: switch to tx-fifo
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when s_txprep0 => -- s_txprep0: switch to tx-fifo
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ififo_ce := '1';
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ififo_ce := '1';
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ififo := c_txfifo;
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ififo := c_txfifo;
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n.state := s_txprep1;
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n.state := s_txprep1;
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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-- rx pipe handling
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idata_cei := r.rxpipe1;
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n.rxpipe2 := r.rxpipe1;
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irxfifo_ena := r.rxpipe2;
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-- chunk counter handling
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-- chunk counter handling
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if cc_clr = '1' then
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if cc_clr = '1' then
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n.ccnt := (others=>'1');
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n.ccnt := (others=>'1');
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elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
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elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
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n.ccnt := slv(unsigned(r.ccnt) - 1);
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n.ccnt := slv(unsigned(r.ccnt) - 1);
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