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-- $Id: nexys2_fusp_dummy.vhd 338 2010-11-13 22:19:25Z mueller $
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-- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: nexys2 minimal target (base; serport loopback)
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-- Description: nexys2 minimal target (base; serport loopback)
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- To test: tb_nexys2
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-- To test: tb_nexys2
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
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-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-26 433 1.2 use nxcramlib
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-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
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-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
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-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
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-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
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-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
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-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
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-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.nexys2lib.all;
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use work.nxcramlib.all;
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entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
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entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
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-- implements nexys2_fusp_aif
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-- implements nexys2_fusp_aif
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port (
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port (
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I_CLK50 : in slbit; -- 50 MHz board clock
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I_CLK50 : in slbit; -- 50 MHz board clock
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O_CLKSYS : out slbit; -- DCM derived system clock
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O_CLKSYS : out slbit; -- DCM derived system clock
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I_RXD : in slbit; -- receive data (board view)
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- s3 switches
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I_SWI : in slv8; -- n2 switches
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I_BTN : in slv4; -- s3 buttons
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I_BTN : in slv4; -- n2 buttons
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O_LED : out slv8; -- s3 leds
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O_LED : out slv8; -- n2 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
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O_MEM_ADDR : out slv23; -- cram: address lines
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16; -- cram: data lines
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IO_MEM_DATA : inout slv16; -- cram: data lines
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O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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);
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);
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O_CLKSYS <= I_CLK50; -- use 50 MHz clock
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O_CLKSYS <= I_CLK50; -- use 50 MHz clock
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O_TXD <= I_RXD; -- loop back
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O_TXD <= I_RXD; -- loop back
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O_FUSP_TXD <= I_FUSP_RXD;
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O_FUSP_TXD <= I_FUSP_RXD;
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O_FUSP_RTS_N <= I_FUSP_CTS_N;
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O_FUSP_RTS_N <= I_FUSP_CTS_N;
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CRAM : n2_cram_dummy -- connect CRAM to protection dummy
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CRAM : nx_cram_dummy -- connect CRAM to protection dummy
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port map (
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port map (
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_ADV_N => O_MEM_ADV_N,
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O_MEM_ADV_N => O_MEM_ADV_N,
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O_MEM_CLK => O_MEM_CLK,
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O_MEM_CLK => O_MEM_CLK,
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O_MEM_CRE => O_MEM_CRE,
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O_MEM_CRE => O_MEM_CRE,
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I_MEM_WAIT => I_MEM_WAIT,
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I_MEM_WAIT => I_MEM_WAIT,
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O_FLA_CE_N => O_FLA_CE_N,
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O_MEM_ADDR => O_MEM_ADDR,
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O_MEM_ADDR => O_MEM_ADDR,
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IO_MEM_DATA => IO_MEM_DATA
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IO_MEM_DATA => IO_MEM_DATA
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);
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);
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O_FLA_CE_N <= '1'; -- keep Flash memory disabled
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end syn;
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end syn;
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