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-- $Id: tb_nexys2_fusp.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: tb_nexys2_fusp.vhd 339 2010-11-22 21:20:51Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: tb_nexys2_fusp - sim
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-- Module Name: tb_nexys2_fusp - sim
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-- Description: Test bench for nexys2 (base+fusp)
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-- Description: Test bench for nexys2 (base+fusp)
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--
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--
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-- Dependencies: vlib/rri/tb/rritb_core
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-- Dependencies: vlib/rri/tb/rritb_core_dcm
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-- tb_nexys2_core
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-- tb_nexys2_core
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-- vlib/serport/serport_uart_rxtx
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-- vlib/serport/serport_uart_rxtx
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-- nexys2_fusp_aif [UUT]
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-- nexys2_fusp_aif [UUT]
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--
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--
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-- To test: generic, any nexys2_fusp_aif target
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-- To test: generic, any nexys2_fusp_aif target
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4; ghdl 0.26
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-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
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-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
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-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
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-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity tb_nexys2_fusp is
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entity tb_nexys2_fusp is
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end tb_nexys2_fusp;
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end tb_nexys2_fusp;
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architecture sim of tb_nexys2_fusp is
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architecture sim of tb_nexys2_fusp is
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signal CLK : slbit := '0';
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signal CLKOSC : slbit := '0';
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signal CLKSYS : slbit := '0';
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signal RESET : slbit := '0';
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signal RESET : slbit := '0';
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signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
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signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
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signal RXDATA : slv8 := (others=>'0');
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signal RXDATA : slv8 := (others=>'0');
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signal RXVAL : slbit := '0';
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signal RXVAL : slbit := '0';
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signal R_PORTSEL : slbit := '0';
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signal R_PORTSEL : slbit := '0';
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constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
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constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
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constant clock_period : time := 20 ns;
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constant clockosc_period : time := 20 ns;
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constant clock_offset : time := 200 ns;
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constant clockosc_offset : time := 200 ns;
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constant setup_time : time := 5 ns;
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constant setup_time : time := 5 ns;
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constant c2out_time : time := 10 ns;
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constant c2out_time : time := 9 ns;
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begin
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begin
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TBCORE : rritb_core
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TBCORE : rritb_core_dcm
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generic map (
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generic map (
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CLK_PERIOD => clock_period,
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CLKOSC_PERIOD => clockosc_period,
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CLK_OFFSET => clock_offset,
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CLKOSC_OFFSET => clockosc_offset,
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SETUP_TIME => setup_time,
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SETUP_TIME => setup_time,
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C2OUT_TIME => c2out_time)
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C2OUT_TIME => c2out_time)
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port map (
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port map (
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CLK => CLK,
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CLKOSC => CLKOSC,
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CLKSYS => CLKSYS,
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RX_DATA => TXDATA,
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RX_DATA => TXDATA,
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RX_VAL => TXENA,
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RX_VAL => TXENA,
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RX_HOLD => RX_HOLD,
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RX_HOLD => RX_HOLD,
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TX_DATA => RXDATA,
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TX_DATA => RXDATA,
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TX_ENA => RXVAL
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TX_ENA => RXVAL
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IO_MEM_DATA => IO_MEM_DATA
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IO_MEM_DATA => IO_MEM_DATA
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);
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);
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UUT : nexys2_fusp_aif
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UUT : nexys2_fusp_aif
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port map (
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port map (
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CLK => CLK,
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I_CLK50 => CLKOSC,
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O_CLKSYS => CLKSYS,
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I_RXD => I_RXD,
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I_RXD => I_RXD,
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O_TXD => O_TXD,
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O_TXD => O_TXD,
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I_SWI => I_SWI,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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I_BTN => I_BTN,
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O_LED => O_LED,
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O_LED => O_LED,
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UART : serport_uart_rxtx
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UART : serport_uart_rxtx
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generic map (
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generic map (
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CDWIDTH => CLKDIV'length)
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CDWIDTH => CLKDIV'length)
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port map (
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port map (
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CLK => CLK,
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CLK => CLKSYS,
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RESET => UART_RESET,
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RESET => UART_RESET,
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CLKDIV => CLKDIV,
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CLKDIV => CLKDIV,
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RXSD => UART_RXD,
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RXSD => UART_RXD,
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RXDATA => RXDATA,
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RXDATA => RXDATA,
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RXVAL => RXVAL,
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RXVAL => RXVAL,
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proc_moni: process
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proc_moni: process
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variable oline : line;
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variable oline : line;
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begin
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begin
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loop
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loop
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wait until CLK'event and CLK='1';
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wait until CLKSYS'event and CLKSYS='1';
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wait for c2out_time;
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wait for c2out_time;
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if RXERR = '1' then
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if RXERR = '1' then
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writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
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writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
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writeline(output, oline);
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writeline(output, oline);
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